Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect

Dept. of Electr. Eng., National Taiwan Univ.Kuo, J.B.J.B.KuoSun, E.C.E.C.SunLin, M.T.M.T.LinKuoJB2007-04-192018-07-062007-04-192018-07-062003-11http://ntur.lib.ntu.edu.tw//handle/246246/200704191002917application/pdf356400 bytesapplication/pdfen-USAnalysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effectjournal article10.1109/EDMO.2003.1259988http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191002917/1/01259988.pdf