Lu, C. L.C. L.LuChuang, C. H.C. H.ChuangHuang, C. H.C. H.HuangLin, S. C.S. C.LinChang, Y. H.Y. H.ChangLai, W. Y.W. Y.LaiChiu, M. H.M. H.ChiuMING-HAN LIAOChang, S. Z.S. Z.Chang2023-08-282023-08-282023-01-01978486348806907431562https://scholars.lib.ntu.edu.tw/handle/123456789/634794Different from Chip on Wafer stacking technology, Wafer on Wafer (WoW) stacking can provide a tighter pitch and higher interconnect density with higher through-put. The difficulty for WoW stacking is on wafer surface and edge treatment. In this work, a 4-layer WoW stacking architecture on 12 -inch wafers with hybrid bonding/bump-less and through-silicon-via (TSV) middle techniques for enabling various 3D integration has been demonstrated and proposed. It projects > 15 % form factor and > 10 % interconnection resistance reduction than typical scheme. Low process temperature (180°C-250°C) is implemented for whole stacking process. Depending on different applications, both of wafers by Face to Face (F2F) and Face to Back (F2B) stacking processes are developed. For bump-less HBM-like structure, it needs special temporary bond and de-pond process for F2B bonding. F2F bonding can present a high dense interconnection for logic to memory AI computing application. The results of 4 layers (TSV x 3 and hybrid bond interface x 3) show that interconnection resistance is < 0.25 Ω per loop. It contains 17Kea of TSVs (5 E 3 / mm2) and 230Kea of hybrid bond pads (2 E 5 / mm2). From the eye-diagram and insertion loss simulation, hybrid bond/bump-less scheme leads to ∼ 40 % performance improvement than it in the bump scheme.conference paper10.23919/VLSITechnologyandCir57934.2023.101853082-s2.0-85167627146https://api.elsevier.com/content/abstract/scopus_id/85167627146