A bipartition-codec architecture to reduce power in pipelined circuits

Shanq-Jang RuanRung-Ji ShangFeipei LaiKun-Lin TsaiFEI-PEI LAI2018-09-102018-09-102001-02http://scholars.lib.ntu.edu.tw/handle/123456789/294599A bipartition-codec architecture to reduce power in pipelined circuitsjournal article10.1109/43.9084772-s2.0-0035248598WOS:000167370300013