Dept. of Electr. Eng., National Taiwan Univ.Ruan, Shanq-JangShanq-JangRuanNaroska, EdwinEdwinNaroskaChang, Yen-RenYen-RenChangHo, Chia-LinChia-LinHoFEI-PEI LAI2018-09-102018-09-102002-10https://www.scopus.com/inward/record.uri?eid=2-s2.0-84948971816&doi=10.1109%2fAPCCAS.2002.1115096&partnerID=40&md5=7753988f5ab0627333d543f617765946Energy consumption has recently emerged as one of the most critical design constraints. It directly relates to the operating time of a portable device. Most researches on pipelined circuits address the optimization of logic blocks to achieve low power. Among the power reduction techniques, the bipartition approach is comparatively effective as it partitions a given circuit into two subcircuits such that only a selected subcircuit is activated at a time, hence reducing unnecessary signal transitions. However operation time of a system is correlated to energy dissipation rather than power dissipation. In this paper, we propose a bipartition algorithm which aims to reduce switching probabilities such that the energy dissipation of combinational blocks as well as pipelined registers are reduced. Transistor-level simulation results show that our proposed algorithm reduces not only the power dissipation but also delay for most of the benchmark circuits. © 2002 IEEE.application/pdf418850 bytesapplication/pdfCircuit synthesis; Computer architecture; Design engineering; Energy consumption; Energy dissipation; Logic devices; Partitioning algorithms; Power dissipation; Power engineering and energy; Registers[SDGs]SDG7Algorithms; Computer architecture; Delay circuits; Electric losses; Energy dissipation; Energy utilization; Logic devices; Low power electronics; Optimization; Circuit synthesis; Design Engineering; Partitioning algorithms; Power engineering and energies; Registers; Logic circuitsconference paper10.1109/APCCAS.2002.11150962-s2.0-84948971816