臺灣大學: 電信工程學研究所黃天偉楊弘源Yang, Hong-YuanHong-YuanYang2013-03-272018-07-052013-03-272018-07-052012http://ntur.lib.ntu.edu.tw//handle/246246/252632本論文研究方向是探討金氧互補式半導體製程上之被動式汲極混波器的相關設計原理、電路實現的最佳化、與系統應用的可行性。 隨著無線網路的速率增長趨勢，未來將邁向百億位元(10-Gigabits)的資料傳輸量，因毫米波頻段提供極寬之頻譜頻寬，已經成為未來無線傳輸的主要可利用的頻譜資源之一，這也開啟目前許多毫米波通訊系統的相關研究。對於現代的無線接收機的組成元件中，一個具有好的轉換增益以及低直流功耗的混波器是非常重要的。因此在這些應用中，被動式混波器架構是一個降低功耗的選擇。然而被動式混波器的高轉換損耗一直是這類混波器的主要缺點。近年來，相關研究文獻中有人提出使用在金氧互補式半導體製程上實現被動式汲極混波器架構可獲得極佳轉換效率。因此在本論文中主要是去研究和討論上述的特性，並且比較不同電路架構的汲極混波器設計來深入探討金氧互補式半導體製程上之被動式汲極混波器。 本論文主要是先由金氧互補式半導體製程上之被動式汲極混波器工作原理為出發點，進而討論其相關特性。藉由因偏壓調整而影響之參數，與時變的輸出中頻電流的模擬結果，我們確認了電晶體閘極偏壓與被動式汲極混波器的轉換損耗之間的關係。接著，我們利用泰勒級數展開式來推導，並提出了一種對於被動式汲極混波器之電晶體閘極偏壓的最佳選擇方法。由此種數學公式推導出之電晶體閘極最佳偏壓，與先前電路模擬的結果一致，因此不但互相驗證了數學公式推導與電路模擬的結果，並且簡化了金氧互補式半導體製程上之被動式汲極混波器的設計流程。 為了改善已發表之金氧互補式半導體製程被動式汲極混波器的操作頻寬，我們提出了一種分散式汲極混波器的架構。此外我們也分析了此分散式混波器閘極傳輸線閘極傳輸線與汲極傳輸線，並用於決定分散式混波器的級數與所使用電晶體的大小，以達成同時兼顧最大可操作頻寬與轉換效率。而根據分散式混波器架構具有寬頻匹配的特性，我們亦利用此混波器來討論常見的電阻式混波器與被動式汲極混波器之間的差異。藉由實驗結果，我們對於兩種混波器架構之間的差異與設計的取捨提出了討論。 經由上述的分散式汲極混波器，金氧互補式半導體製程被動式汲極混波器的低轉換損耗的特性得到了驗證。我們接下來為了實際上系統應用的考量，提出了一種新型的雙平衡式被動汲極混波器架構。利用雙平衡式架構對稱的特點，此混波器改善了目前已發表之汲極混波器架構上所存在的隔離度不足之問題。此外，一個利用馬遜不平衡轉換器所組成的阻抗轉換網路被提出並用於此混波器的設計之中。相較於一些已知的環形混波器與星狀混波器架構，我們所提出的雙平衡式被動汲極混波器架構改善了傳統雙平衡式被動混波器的轉換損耗，並且具有小面積與較多中頻選擇的彈性等特點。The purpose of this dissertation is to discuss the operation principles, circuit optimizations, and applicability of the CMOS passive drain-pumped mixer topology. With the trend of wireless networks toward multigigabits transmissions, the millimeter-wave (MMW) band with ultra-broad bandwidth has become one of the major players for future gigabit-wireless transmissions. It also motivates the researches on MMW communication systems. For the modern receiver building blocks, a mixer with good conversion efficiency and low dc power is important. As a result, the passive mixer is one of the candidates for low-power applications. However, the high conversion loss of passive mixers is a serious drawback. Recently, a CMOS passive drain mixer with good conversion efficiency has been reported. This dissertation is to analyze the characteristics of CMOS drain mixers and to implement passive drain-pumped topology using innovative architectures. We begin with the operation principles of a CMOS drain mixer. According to the simulation results of the bias tuning parameters and the time-varying output IF current, the relations between the gate bias and the conversion loss of the mixer are obtained. Using Taylor’s series analysis, a gate bias optimization method for the CMOS drain mixer design is proposed. The analytic formula can predict the optimum gate bias point, which agrees well with the circuit simulation data. It also simplifies the complexities of the CMOS drain mixer design flow. To enhance the operation bandwidth of the CMOS drain mixer, we proposed a distributed drain-pumped topology. For the broad bandwidth and the conversion efficiency, the gate line and the drain line of the distributed mixer is analyzed to determine the gate inductances, drain inductances, device sizes and the number of stage. According to the wideband matching characteristics of distributed mixers, we utilize the mixer to discuss the differences between resistive mixers and passive drain mixers. Based on the experimental results, the design tradeoffs and differences of two mixers’ configurations are describes. Since the conversion efficiency and the operation bandwidth of the CMOS passive drain-pumped topology have been investigated through the distributed architecture, we proposed another CMOS drain mixer using the doubly balanced architecture for the receiver applications. With the symmetric configuration of the doubly balanced architecture, the proposed mixer overcomes the port-to-port isolations limitation in the other single-stage CMOS drain mixer. In addition, a concept of impedance transformations using a Marchand balun network is described and successfully implemented in the mixer design. As compared to the reported resistive mixer topologies, like ring mixers and star mixers, the proposed doubly balanced drain mixer improves the conversion loss with a compact chip size, wide IF frequency selections and a moderate LO power requirement.8260731 bytesapplication/pdfen-US混波器毫米波電路射頻mixerMMICRFthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/252632/1/ntu-101-D96942008-1.pdf