Syu, J.-R.J.-R.SyuKao, K.-Y.K.-Y.KaoLin, K.-Y.K.-Y.LinKUN-YOU LIN2018-09-102018-09-102012http://www.scopus.com/inward/record.url?eid=2-s2.0-84874421985&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/372336A V-band frequency quadrupler implemented in 90-nm LP CMOS process is proposed with 3-dBm output power. This frequency quadrupler consists of a 30-GHz frequency doubler, a 30-GHz buffer amplifier and a 60-GHz frequency doubler. The measured maximum conversion gain is 3 dB at 66 GHz, and the 3-dB bandwidth is from 62 to 70 GHz under 0-dBm input drive power. Harmonic suppressions of the fundamental, the second and the third harmonics are all better than 30 dB. The dc power consumption is 53.4 mW, and the chip size is 0.57 × 0.59 mm 2.CMOSdoublerquadruplerV-band[SDGs]SDG7conference paper10.1109/APMC.2012.64215452-s2.0-84874421985