Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous Triggering

CHIEN-MO LIY. C. HuangM. H. TsaiW. S. DingJ. C. M. LiM. T. ChangM. H. TsaiC. M. TsengH. C. LiCHIEN-MO LI2018-09-102018-09-102013-01http://scholars.lib.ntu.edu.tw/handle/123456789/381709Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous Triggeringjournal article10.1109/tcad.2012.22287412-s2.0-84875617890WOS:000317001200015