Chung, Jung-TaoJung-TaoChungHsu, Keng-LiKeng-LiHsuLi, Jyun-HaoJyun-HaoLiTu, Shao-YuShao-YuTuLin, Kun-YouKun-YouLinCHAO-HSIN WU2025-11-212025-11-212025-10-2700189480https://www.scopus.com/record/display.uri?eid=2-s2.0-105020438576&origin=resultslisthttps://scholars.lib.ntu.edu.tw/handle/123456789/733928This article presents a design methodology for realizing a high-efficiency, two-stage, two-way gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) power amplifier (PA) targeting sixth-generation (6G) FR3-band applications under handset-compatible supply voltage. A thermal simulation model is developed to accurately predict the junction temperature of the HBT devices, enabling the verification of thermal management strategies and optimization of the power stage layout. To enhance design flexibility, the optimized GaAs HBT power stage chip is separated from the external matching components, enabling flexible impedance matching across the 8–15-GHz frequency range for application-specific tuning. A proof-of-concept PA operating at 12 GHz is designed and implemented using a 1.6- \mu m GaAs HBT technology with a supply voltage of 6.5 V. The PA comprises two gain stages, with the output stage configured as two parallelized power-stage units, each consisting of 16 transistors. Under continuous-wave (CW) operation, the PA achieves a peak output power of 34.4 dBm and a power-added efficiency (PAE) of 50%.falseFlip-chip (FC)gallium arsenide (GaAs) heterojunction bipolar transistor (HBT)power amplifiers (PAs)power stage optimizationpower-added efficiency (PAE)sixth-generation (6G) FR3thermal managementwire bonding (WB)wireless handset[SDGs]SDG7journal article10.1109/tmtt.2025.36167862-s2.0-105020438576