Dept. of Electr. Eng., National Taiwan Univ.Wang, Y.S.Y.S.WangLIANG-HUNG LU2007-04-192018-07-062007-04-192018-07-062005-0100135194http://ntur.lib.ntu.edu.tw//handle/246246/200704191001030https://www.scopus.com/inward/record.uri?eid=2-s2.0-13844255496&doi=10.1049%2fel%3a20057230&partnerID=40&md5=90a03e91418283fd2743a97f40d305dbA variable-gain low-noise amplifier (LNA) suitable for low-voltage and low-power operation is designed and implemented in a standard 0.18 μm CMOS technology. With a current-reused topology, the common-source gain stages are stacked for minimum power dissipation while achieving high small-signal gain. The fully integrated 5.7 GHz LNA exhibits 16.4 dB gain, 3.5 dB noise figure and 8 dB gain tuning range with good input and output return losses. The LNA consumes 3.2 mW DC power from a supply voltage of 1 V A gain/power quotient of 5.12 dB/mW is achieved in this work.application/pdf464756 bytesapplication/pdfen-USCMOS integrated circuits; Electric impedance; Energy dissipation; Energy utilization; Gain control; MOSFET devices; Resonance; Signal processing; Spurious signal noise; Topology; Tuning; Low-noise amplifier (LNA); Low-power operation; Power quotient; Small-signal gain; Amplifiers (electronic)journal article10.1049/el:200572302-s2.0-13844255496http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191001030/1/01393475.pdf