指導教授：陳少傑臺灣大學：電子工程學研究所曾崇銘Tseng, Chung-MingChung-MingTseng2014-11-302018-07-102014-11-302018-07-102014http://ntur.lib.ntu.edu.tw//handle/246246/263872隨著製程進步，純類比電路越來越困難設計，遭遇到嚴重的表現取捨，使得高表現低功耗難以達成。因此本論文借助校正系統的幫助，來使類比電路提高表現，去達成高表現低功耗的目標。在本論文中我們實現了一個高速且低功率的十位元管線式類比數位轉換器和一個應用在時脈系統中高速抽載下的低電壓穩壓器。高速且低功率的十位元管線式類比數位轉換器結合了我們提出的混合式校正方法來達到比他人校正方法更快的校正速度達近2倍且省下數位電路面積。而用在時脈系統中高速抽載下的低電壓穩壓器，結合提出的時脈補償機制，使其穩壓效能比傳統穩壓器更快穩定達3倍以上。 根據量測的結果，結合我們校正系統的類比數位轉換器晶片在10MS/s的取樣頻率下，對於1MHz的輸入頻率下SNDR為53.5dB，SFDR為70dB。而在還沒校正前，電路的SNDR和SFDR僅有28.5dB和32.6dB。當時脈升至200MS/s時，SNDR及SFDR分別降為46.1B及60.8dB。在200MS/s的操作頻率之下，電路的消耗功率為20.4mW。而另一顆晶片--低電壓穩壓器晶片在時脈為10MHz的系統下(抽載時變率100MHz)的情況下達到穩定僅需8ns，在時脈為20MHz的系統下(抽載時變率200MHz)的情況下達到穩定僅需11.6ns。CONTENTS 口試委員會審定書 # 誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES ix LIST OF TABLES xiv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Power-Line Communication System 1 1.3 Thesis Organization 3 Chapter 2 Fundamental of Analog-to-Digital Converters and Low Drop-Out Regulator 4 2.1 Introduction 4 2.2 Architectures of Analog-to-Digital Converters 4 2.2.1 Flash ADC 4 2.2.2 Successive-Approximation (SAR) ADC 6 2.2.3 Two Step and Sub-Ranging ADC 7 2.2.4 Pipelined ADC [2] 8 2.2.5 Cyclic ADC 9 2.2.6 Delta-Sigma ADC 10 2.3 Linear Regulators 10 Chapter 3 The Proposed Pipelined Analog-to-Digital Converter with Hybrid-Calibration Method 13 3.1 Introduction 13 3.2 Prior Work 14 3.3 Proposed Hybrid-Calibration Method 15 3.3.1 Idea of Hybrid-Calibration Method 15 3.3.2 The Main Architecture of Proposed ADC 17 3.3.3 The Analog-type Nonlinear-Calibration Circuits for Hybrid-calibration Method in Proposed ADC 18 3.4 Circuit Implementation 21 3.4.1 1.5 bits/stage Pipelined ADC Architecture 21 3.4.2 Delay Element Circuit 25 3.4.3 SHA-less Network With 25% Clock Circuit 26 3.4.4 MDAC with Proposed Non-Linear Circuit 28 3.4.5 Bootstrapped Switch[17] 30 3.4.6 Switch Technique 32 3.4.7 Capacitor Size Selection 34 3.4.8 Specification and Structure of Op-amp 36 3.4.9 Dynamic Comparator [18] 38 3.4.10 Sub-ADC and DAC 39 3.4.11 Clock Generator 39 3.4.12 Digital Calibration [7][8][9][10] 42 3.5 Layout & Post-Layout Simulation 44 3.5.1 Layout 44 3.5.2 Post-Layout Simulation Results 46 3.6 Experimental Results 52 3.6.1 Measurement setup 52 3.6.2 PCB Design 53 3.6.3 10-bit 200MS/s Pipelined ADC Measurement Result 54 3.7 Performance Diagnosis 62 3.7.1 Noise Consideration and Layout Modification 63 3.7.2 THD Improvement with Corner Consideration and Layout Modification 64 3.7.3 PCB Modification for Noise Analysis 65 3.8 Summary 66 Chapter 4 A LDO with Proposed Clock-Compensate Technique 68 4.1 Introduction 68 4.2 Motivation 68 4.3 Proposed Clock-Compensate Technique 70 4.3.1 Idea of Proposed Clock-Compensate Technique 70 4.3.2 Proposed Triangular Pulse Generator With 12% Loading Time Error Tolerance and 60-100mA Peak Current Variation Designed Approach 72 4.3.3 Accelerate the Speed of the Original LDO’s Op-Amp and solve the Op-Amp Offset 74 4.4 Other Circuits Implement 75 4.4.1 Op-Amp 75 4.4.2 Test Circuit 75 4.4.3 Whole Circuits in Chip 76 4.5 Layout & Post-Layout Simulation 77 4.5.1 Layout 77 4.5.2 Post-Layout Simulation (R+C+CC) Results 79 4.6 Experimental Result 84 4.7 Performance Diagnosis 89 4.8 Summary 89 Chapter 5 Conclusion and Future Work 91 5.1 Conclusion 91 5.2 Future Work 92 Reference 942850927 bytesapplication/pdf論文公開時間：2019/07/22論文使用權限：同意有償授權(權利金給回饋學校)類比數位轉換器thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/263872/1/ntu-103-R00943017-1.pdf