Zero-Skew Clock-Tree Optimization with Buffer-Insertion/Sizing and Wire-Sizing

Jeng-Laing TsaiTsung-Hao ChenCHUNG-PING CHEN2018-09-102018-09-102004-04http://scholars.lib.ntu.edu.tw/handle/123456789/310820Zero-Skew Clock-Tree Optimization with Buffer-Insertion/Sizing and Wire-Sizingjournal article10.1109/TCAD.2004.8258752-s2.0-2342423095WOS:000220476400012