A Novel 0.7V Two-Port 6T SRAM Memory Cell Structure with Single-Bit-Line Simultaneous Read-and-Write Access (SBLSRWA) Capability using Partially Depleted SOI Dynamic-Threshold Technique

S. C. LiuJ. B. KuoJAMES-B KUO2018-09-102018-09-101999-10http://scholars.lib.ntu.edu.tw/handle/123456789/351951[SDGs]SDG7A Novel 0.7V Two-Port 6T SRAM Memory Cell Structure with Single-Bit-Line Simultaneous Read-and-Write Access (SBLSRWA) Capability using Partially Depleted SOI Dynamic-Threshold Techniqueconference paper10.1109/soi.1999.819860