Hsu, Yu-WeiYu-WeiHsuLin, Yu-TungYu-TungLinChiang, Nien-EnNien-EnChiangChen, Shao-HengShao-HengChenChiu, Ying-ZhanYing-ZhanChiuHsu, Chen-HsunChen-HsunHsuWei, Ting-HuaTing-HuaWeiLee, Sin-YueSin-YueLeeSu, Zi-QuanZi-QuanSuChiang, Hung-LiHung-LiChiangNi, I-ChihI-ChihNiLee, Tsung-EnTsung-EnLeeWu, Chih-IChih-IWu2026-03-262026-03-262026-01-2307413106https://www.scopus.com/record/display.uri?eid=2-s2.0-105028524613&origin=resultslisthttps://scholars.lib.ntu.edu.tw/handle/123456789/736815This work demonstrates the two-step elevated-temperature atomic layer deposit (ALD) process of bilayer ZrOx/HfOx relatively higher-κ dielectrics reported on chemical vapor deposit (CVD) monolayer (1L) WSe2 for top-gate dielectric. Top-gated 1L-WSe2 pFETs with a low subthreshold swing (S.S. ∼60 mV/dec) are achieved at a low equivalent oxide thickness (EOT) of 0.8 nm. By scaling the physical thickness of this two-step bilayer ZrOx/HfOx dielectric with the pinhole-free AlOx nucleation layer down to 2 nm, the proposed gate stack exhibits a high effective dielectric constant (ϵeff ∼ 14) and strong reliability (breakdown field EBD ∼ 21 MV/cm) at the scaled EOT. This breakthrough in gate dielectric integration on p-type 1L-WSe2 enables balanced n/p performance for 2D-channel devices and enhances the feasibility of future low-power consumption CMOS applications.false2D gate stacksdielectric engineer and low power consumptioneffective oxide thicknessmonolayer tungsten diselenidetop-gate devicesTwo-dimensional materialjournal article10.1109/led.2026.36575602-s2.0-105028524613