電機資訊學院: 電子工程學研究所指導教授: 李建模王英旭Wang, Ying-HsuYing-HsuWang2017-03-062018-07-102017-03-062018-07-102015http://ntur.lib.ntu.edu.tw//handle/246246/276142由於有許多狀態保持元素存在於非同步電路，許多錯誤需要兩組圖樣測試。本論文提出一個針對雙軌非同步電路的兩組圖樣測試技術。我們的可測試設計是根據一個完全掃描且無需時脈的雙軌掃描技術(DR-scan)。為了降低測試時間，我們選擇一個最小集合的測試配置。如果有多於一個選擇測試配置，我們需要將掃描栓鎖器分割成多條掃描鍊。為了使用兩組圖樣測試，我們利用頂點著色來分隔電路。使用本文提出的測試技術，我們可以使用傳統完全掃描的自動測試圖樣產生器去產生高測試涵蓋率的兩組圖樣測試。實驗結果顯示，平均而言，我們的測試技術可以使許多非同步電路達到高於92%的測試涵蓋率。Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This thesis presents a two-pattern test methodology for dual-rail asynchronous circuits. Our design for testability (DFT) is based on a full-scan, clock-less, Dual-rail scan (DR-scan) technique. To reduce test time, we choose a minimum set of selected test configurations. If there are more than one selected test configuration, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve higher than 92% average test coverage for various asynchronous circuits.4460312 bytesapplication/pdf論文公開時間: 2015/12/1論文使用權限: 同意有償授權(權利金給回饋本人)非同步電路雙軌邏輯可測試設計自動測試圖樣產生器兩組圖樣測試Asynchronous circuitsDual-rail logicDesign for testabilityAutomatic test pattern generationTwo-pattern teststhesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/276142/1/ntu-104-R02943156-1.pdf