Hwang, Huei-YanHuei-YanHwangJUN-CHAU CHIENChen, Tai-YuanTai-YuanChenLIANG-HUNG LU2020-06-112020-06-112006https://scholars.lib.ntu.edu.tw/handle/123456789/498233https://www.scopus.com/inward/record.uri?eid=2-s2.0-33845521027&doi=10.1109%2fLMWC.2006.885641&partnerID=40&md5=afa6d1a90a366748826099832dc6c490A tunable transimpedance amplifier (TIA) is presented in this letter. By incorporating a mechanism for gain and bandwidth tuning, the TIA can be adjusted to achieve optimum circuit performance with a lowest bit-error-rate (BER) for high-speed applications. The proposed circuit is implemented in a 0.18-μm CMOS process. Consuming a dc power of 34 mW from a 2.0-V supply voltage, the fabricated TIA exhibits a variable - 3-dB bandwidth from 3.9 to 7.6 GHz while maintaining a transimpedance gain of 52 dBΩ. With a 7.5-Gb/s 2 31 -1 pseudo-random bit sequence, the measured input sensitivity of the TIA is - 19 dBm at a BER of 10 -12. © 2006 IEEE.Bit-error-rate (BER); Input sensitivity; Intersymbol interference (ISI); Optical receiver; Regulated cascode; Total integrated noise; Transimpedance amplifier (TIA); Tunable bandwidthOptical receivers; Total integrated noise; Transimpedance amplifier (TIA); Tunable bandwidth; Bandwidth; Bit error rate; CMOS integrated circuits; Electric impedance; Gain control; Intersymbol interference; Power amplifiersjournal article10.1109/LMWC.2006.8856412-s2.0-33845521027WOS:000242925100021