臺灣大學: 電信工程學研究所王暉郭京霖Kuo, Jing-LinJing-LinKuo2013-03-272018-07-052013-03-272018-07-052012http://ntur.lib.ntu.edu.tw//handle/246246/252594本研究使用65奈米CMOS製程研發60-GHz四單元相位陣列天線收發器之系統封裝 (system in package，SiP) 模組。此系統包含功率放大器 (power amplifier，PA)、可變增益低雜訊放大器 (variable gain low noise amplifier，VGLNA)、4:1威爾金森功率分/合網路 (Wilkinson power combining/dividing network)、四位元切換型相移器 (switching type phase shifters，STPS)、相位補償之可變增益放大器 (variable gain amplifier，VGA)、數位控制介面(digital control interface，DCI)、六位元數位類比轉換器 (digital-to-analog converter，DAC)、靜電放電(electrostatic discharge，ESD)保護電路以及偏壓電路(bias circuit)。收發晶片使用覆晶技術直接黏著於低溫共燒陶瓷(low temperature co-fired ceramic，LTCC)基板上，並以填底 (underfill) 材料加強封裝結構。此SiP模組可直接使用錫球或鎊線組裝於印刷電路板 (printed circuit board, PCB)上使用。從天線饋入端至晶片輸出入端RF訊號傳輸路徑經由適當的分析與設計，可有效降底整體傳輸路徑的損耗，同時亦可大幅提升工作頻寬。而天線陣列則直接做在模組與晶片相接的另外一面，使用了空腔負載的結構使得天線單元的頻寬可以超過20%，並以連通柱為基礎的皺褶(corrugated)結構降低天線單元間的耦合至-15 dB以下。 此2x2收發相位陣列與四個天線單元構裝於低溫共燒陶瓷(low temperature co-fired ceramic，LTCC)模組中，並成功展示波束切換之功能，此波束切換功能可完全由數位控制介面控制。四單元發射機(transmitter, Tx)陣列每通道之P1dB為5 dBm；四單元接收陣列每通道之平均增益則為25 dB。Tx陣列使用1 V電源，功耗為400 mW，接收機(receiver, Rx)陣列使用1.8 V及1 V電源，功耗則為180 mW。Rx及Tx晶片分別使用3.74 mm2及4.18 mm2之面積。模擬與量測一致性良好。就吾人所知，此為V頻段第一個不需高/低頻轉換器(up/down converter)而能直接量測相位陣列系統場型之量測結果。The 60-GHz 4-element phased-array transmit/receive (TX/RX) system-in-package (SiP) antenna modules in 65nm CMOS technology are presented. The design is based on the all-RF architecture with power amplifier (PA), variable gain low noise amplifier (VGLNA), 4:1 Wilkinson power combining/ dividing (PC/PD) network, 4-bits RF switching type phase shifters (STPS), phase compensated variable gain amplifier (VGA), digital control interface (DCI), 6-bits unary digital-to-analog converter (DAC), electrostatic discharge (ESD) protection, and bias circuit. The 2x2 TX/RX phased arrays have been packaged with 4 antennas in a low temperature co-fired ceramic (LTCC) module. The 60-GHz SiP module packaging technology has also been developed. The Tx/Rx ICs are bonded onto low temperature co-fired ceramic substrates through flip-chip bonding and underfill process, which can be assembled onto printed circuit boards with bond wires or solder balls for further usage. Electrical characteristics of the RF signal traces from IC to antenna array are investigated to lower the transmission loss. The antenna array is designed on the other side opposite to the flipped chip side, by using the backed cavity to achieve more than 20% bandwidth and high isolation. The mutual coupling of antenna elements is reduced by incorporating the via-based corrugation between antenna elements and the interleaved topology for the array layout. The measured couplings of adjacent elements were below -15 dB. The entire 2x2 beam steering functions are digitally controllable, and the individual registers are integrated at each front-end to enable beam steering through the DCI. The four-element TX array results in an output P1dB of 5 dBm per channel. The four-element RX array results in an average gain of 25 dB per channel. The four-element array consumes 400 mW in the TX from 1-V supply voltage and 180 mW in the RX from 1.8-V and 1-V supply voltage, and occupies an area of 3.74 mm2 in TX IC and 4.18 mm2 in RX IC. Good agreement between simulated and measured array pattern is demonstrated. To the author’s knowledge, this is the first demonstration of on-wafer V-band phased array system pattern measurement without the up/down converter.7861088 bytesapplication/pdfen-US金氧半場效電晶體相位陣列60-GHzV 頻帶802.11ad系統封裝模組波束成型系統發射機接收機覆晶無線通訊系統。CMOSphased arrayV-bandsystem-in-package (SiP)beamformingtransmitterreceiverflip-chipwireless communication.thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/252594/1/ntu-101-D97942006-1.pdf