An efficient two-level partitioning algorithm for VLSI circuits

Dept. of Electr. Eng., National Taiwan Univ.Cherng, Jong-ShengJong-ShengCherngChen, Soo-JieSoo-JieChenTsai, Chia-ChunChia-ChunTsaiHo, Jan-MingJan-MingHo2007-04-192018-07-062007-04-192018-07-061999-01http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021658application/pdf497314 bytesapplication/pdfen-USAn efficient two-level partitioning algorithm for VLSI circuitsjournal article10.1109/ASPDAC.1999.759712http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021658/1/00759712.pdf