2011-08-012024-05-17https://scholars.lib.ntu.edu.tw/handle/123456789/689242摘要：本計畫預備研發及設計60 Ghz之無線收發系統之接收系統相關單晶積體電路。單晶電路的製作將使用矽（包含矽鍺）或砷化鎵之微波單晶積體電路（MMIC）之製程，此製程將由與國研院晶片中心簽約之代工廠所提供。研製的元件包含低雜訊放大器、射頻切換器、混頻器、IF 放大器，預定會將所研製的元件與子計畫3、4、6整合成一個單晶微波收發機。 在單晶電路設計方面，初始的設計將使用代工廠所提供的元件模型。部份的電路理念，將設計一些混成電路（Hybrid Circuits）來驗證。在元件模型的技術方面，固態元件（二極體及電晶體）及被動元件等工作項目都包含在本計畫內。固態元件的模型工作包括元件直流（DC）及射頻的特性分析，以及建立模型。被動元件模型則由理論分析模擬，再經實驗印證。測試用的特別電路元件都將與MMIC的電路，一同設計在同一套光罩組上，而所有的模型都將在量測、印證、以及修改後確認，以利下一次設計的進行。為了達到低功耗接收機的目標，CMOS 製程的電路將會是主要的製程選擇。另外，被動混波器的降頻電路也會考慮用來減少直流的功耗。 本計畫以三年為期，元件模型、電路設計、晶片布局、製作及晶片量測等工作均將進行。第一年將著重於用現有元件模型設計單功能之晶片，並設計一些測試用電路。初步的設計及佈局在第一年中將完成並送交代工廠製作。同時亦將進行某些混成電路實驗來驗證之元件模型及電路設計理念。第二年中，首先會量測第一年的晶片並調整元件模型，這些晶片將用於總計畫中的初步射頻模組設計。此外我們將使用調整後之元件模型設計第二年之晶片。第三年則將嘗試整合單一功能晶片而設計多功能之單晶積體電路，晶片成果將用於最後的射頻模組中。 <br> Abstract: This project is proposing the development and the design of 60-GHz receiver components for wireless transceiver applications using Si (including SiGe) or GaAs-based MMIC process technologies, which are available through commercial foundries. The components will include low noise amplifiers, mixers, RF switches and IF amplifiers, etc. Finally, the components will be integrated with sub-projects 3, 4, 6 into a single chip MMIC transceiver. In the MMIC design portion, we will use the device model provided by the MMIC for the foundries initial design. In order to verify new design concept, some hybrid circuits will be built and tested during the design phase. Regarding the device modeling, both solid-state devices (diode and transistor) models and passive elements will be investigated. The device modeling effort includes device dc, RF characterization and model generation, while the passive element modeling will be exercised via theoretical analysis and then verified by experiments. Test structures for various models will be designed in parallel with the circuit design and placed on the same MMIC mask set such that the models can be verified and then updated for the next iteration. To achieve the goal of low power consumption, CMOS process will be chosen for the main process. Moreover, passive mixer will be considered to reduce the power consumption. In this 3-year project, device modeling, MMIC design, chip layout, fabrication and chip evaluation will all be exercised. For the first year, we will focus on individual single-function components based on existing models. A set of test structures will be designed. The initial design and layout should be completed and sent to foundry for fabrication. Some hybrid MIC experiment will also be conducted to verify device models and circuit design concept. In the second year, we will investigate the measured performance of first iteration chips refine the device models. The first-iteration chips will also be used for the initial RF module design of the main-project. The second iteration design and layout will be finished also. In the third year, besides refining models, higher level integration for a complete up- and down-converters will be attempted. The final chips will be used in the final RF module.單晶毫米波積體電路（MMIC）降頻器升頻器收發模組MMICReceiver ModuleLNAmixerswitch