B. ChungJAMES-B KUO2018-09-102018-09-102008-01https://www.scopus.com/inward/record.uri?eid=2-s2.0-34548505549&doi=10.1016%2fj.vlsi.2007.03.001&partnerID=40&md5=75c47804f1c7c9b618a697a9cd0475f7This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis (STA) technique for designing high-speed low-power SOC applications using 90 nm multi-threshold complementory metal oxide semiconductor (MTCMOS) technology. The cell libraries come in fixed threshold-high Vth for good standby power and low Vth for high speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library. © 2007 Elsevier B.V. All rights reserved.Dual-threshold CMOS; Power optimization; SOC; Static timing analysisGate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Applicationjournal article10.1016/j.vlsi.2007.03.0012-s2.0-34548505549WOS:000250491000003