Ruan, Shanq-JangShanq-JangRuanTsai, Kun-LinKun-LinTsaiNaroska, EdwinEdwinNaroskaFEI-PEI LAI2009-02-272018-07-062009-02-272018-07-062005https://www.scopus.com/inward/record.uri?eid=2-s2.0-30544443434&doi=10.1145%2f1044111.1044114&partnerID=40&md5=628f961b4c3efc424c965d17663039caIn this article, we present a bipartition dual-encoding architecture for low-power pipelined circuits. We exploit the bipartition approach as well as encoding techniques to reduce power dissipation not only of combinational logic blocks but also of the pipeline registers. Based on Shannon expansion, we partition a given circuit into two subcircuits such that the number of different outputs of both subcircuits are reduced, and then encode the output of both subcircuits to minimize the Hamming distance for transitions with a high switching probability. We measure the benefits of four different combinational bipartitioning and encoding architectures for comparison. The transistor-level simulation results show that bipartition dual-encoding can effectively reduce power by 72.7% for the pipeline registers and 27.1% for the total power consumption on average. To the best of our knowledge, it is the first work that presents an in-depth study on bipartition and encoding techniques to optimize power for pipelined circuits. © 2005 ACM.application/pdf92748 bytesapplication/pdfen-USLow-power designjournal article10.1145/1044111.10441142-s2.0-30544443434http://ntur.lib.ntu.edu.tw/bitstream/246246/142056/1/19.pdf