Dept. of Electr. Eng., National Taiwan Univ.Liou, Ming-LuenMing-LuenLiouTZI-DAR CHIUEH2007-04-192018-07-062007-04-192018-07-062000-0502714310http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021467The paper presents a parametric module design framework that is suitable for datapath/DSP soft-IP design. This framework is based on the integration of various frequently used parametric module generators. Under this design framework, system or circuit designers specify the structural information of the modules in C++, and then compile and co-simulate with any C/C++ programs/algorithms. Furthermore, they can manually adjust the simulation model whenever necessary. Once the system design is completed, an efficient gate-level Verilog code can soon be generated automatically. By examining the system functionality using high-level language and automatically translating the design entries into gate-level description, we can easily keep our design effort at system level while maintaining a tight consistency between different levels of abstraction. Therefore the proposed framework yields a fast, robust, and cost-effective solution to high-complexity datapath/DSP module design.application/pdf509096 bytesapplication/pdfen-USAlgorithms; C (programming language); Computational complexity; Computer aided design; Computer simulation; Digital signal processing; Microprocessor chips; Program compilers; VLSI circuits; Verilog codes; Integrated circuit layoutAlgorithms; C (programming language); Computational complexity; Computer aided design; Computer simulation; Digital signal processing; Microprocessor chips; Program compilers; VLSI circuits; Verilog codes; Integrated circuit layoutjournal article10.1109/ISCAS.2000.8562532-s2.0-0033697566http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021467/1/00856253.pdf