Lin H.-CChou TChiu K.-YChung C.-CTsen C.-JCHEE-WEE LIU2023-06-092023-06-092022https://www.scopus.com/inward/record.uri?eid=2-s2.0-85130429316&doi=10.1109%2fVLSI-TSA54299.2022.9770993&partnerID=40&md5=a40f0a9f25fb8466d3d945c9f335f285https://scholars.lib.ntu.edu.tw/handle/123456789/632198RF performance of stacked nanosheet (NS) nFETs is studied and optimized by validated TCAD simulation considering the 6-stack 4-finger transistor array layout and back-end-of-line (BEOL) up to M3 level. As compared to FinFETs, stacked NSs have larger effective width (Weff) under similar parasitic capacitance (Cpar), leading to better RF performance. In this work, the cut-off frequency (fT) and maximum oscillation frequency (fMAX) of Stacked NSs can achieve 435GHz and 405GHz by optimizing gate length (Lg) to 18nm, effective oxide thickness (EOT) to 0.8nm, suspension thickness (Tsus) to 7nm, and floor number (floor#) to 4. © 2022 IEEE.Capacitance; Floors; Silicon; Array layout; Back end of lines; Cut-off frequency (fT); Effective width; Large effective; Parasitics capacitance; Performance optimizations; RF performance; TCAD simulation; Transistor arrays; Nanosheetsconference paper10.1109/VLSI-TSA54299.2022.97709932-s2.0-85130429316