An at-speed test technique for high-speed high-order adder by a 6.4-GHz 64-bit domino adder example

Wang, Y.-S.Y.-S.WangHsieh, M.-H.M.-H.HsiehLi, J.C.-M.J.C.-M.LiCHIEN-MO LICHUNG-PING CHEN2020-06-112020-06-112012https://scholars.lib.ntu.edu.tw/handle/123456789/501065[SDGs]SDG7An at-speed test technique for high-speed high-order adder by a 6.4-GHz 64-bit domino adder examplejournal article10.1109/TCSI.2012.22065032-s2.0-84864569486https://www.scopus.com/inward/record.uri?eid=2-s2.0-84864569486&doi=10.1109%2fTCSI.2012.2206503&partnerID=40&md5=69fb56addc6d44e1ab895f9b8bb242bf