國立臺灣大學電機工程學系暨研究所闕志達2006-07-252018-07-062006-07-252018-07-062001-07-31http://ntur.lib.ntu.edu.tw//handle/246246/7814本文中，根據ETSI 所提出之高速數位用戶 迴路標準，設計一以DMT 作調變之傳收 機。近年來，高速資料傳輸的需求增加， 特別是在網際網路相關的應用中，像是網 路會議、視訊點播、影像電話等。由於全 面鋪設光纖是相當昂貴的，為了在現有的 電話網路上達到寬頻的傳輸，DSL 的技術 便因應而生。在本文中，首先介紹DMT 相 關的理論基礎，並介紹ETSI 所提出之高速 數位用戶迴路標準中之重要參數。在將實 際通訊系統中之非理想特性加以考慮之 下，我們提出一傳收機架構，並驗證其可 以克服用戶迴路上之非理想特性，而為了 實際的硬體實作，利用定點數模擬來決定 架構中重要節點之位元數，在系統效能不 會損失太多的情況下，降低所需電路的複 雜度。最後並以FPGA 驗證系統中之重要 功能方塊。In this paper, a transceiver design for VDSL standard using the DMT(Discrete Multi-Tone) modulation is proposed. The design is based on ETSI VDSL standard, which is for very high speed digital subscriber loop. Recently, the need for high-speed data transmission increases rapidly, especially in the application of net-meeting, video on demand, video phone, etc. The DSL technology is proposed to achieve broadband access by transmitting data on existing telephone network instead of using fiber all the way to the residence, which is more costly. Basic principles of DMT and its related issues are illustrated in the paper. Besides, the important features and parameters of ETSI VDSL standard are also introduced. By taking the non-idealities in the transmission environment into consideration, a transceiver architecture is proposed and verified by functional simulations and is able to combat those impairment in subscriber lines. For hardware implementation, fixed-point simulation of the proposed transceiver architecture was conducted to determine word length of important signals in the architecture with a view to reducing the circuit complexity and resources requirement without incurring too much performance loss. Finally, the main functional blocks are implemented by FPGA to verify their functionality.application/pdf97757 bytesapplication/pdfzh-TW國立臺灣大學電機工程學系暨研究所收發機VDSLDMTtransceiversreporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/7814/1/892218E002080.pdf