陳信樹臺灣大學：電子工程學研究所陳翊青Chen, I-ChingI-ChingChen2007-11-272018-07-102007-11-272018-07-102007http://ntur.lib.ntu.edu.tw//handle/246246/57374本研究是採用兩階段式 (Two-step) 的架構，來實現高速的類比數位轉換器(Analog-to-Digital Converter)。在此論文中提出一個快速穩定的方法 (fast-settling method)來縮短運算放大器的上升時間以及經由重新安排時脈圖來使得電路可以工作的更加有效率。本晶片使用台積電0.13-μm CMOS製程製作，解析度為六位元，操作時脈頻率為1 GS/s，INL為+0.3/-0.3 LSB，DNL為+0.49/-0.49 LSB，在輸入信號頻率為奈奎斯特頻率的情況下，SFDR為49.2dB，SNDR為31.3dB，在1.2伏特的供應電壓下，消耗功率為 50mW。A 1 GS/s 6-bit CMOS two-step ADC using fast-settling method and through timing rearrangement is demonstrated in a standard 0.13-μm CMOS process. The proposed method shortens the slew time of OPAMP in MDAC and the timing arrangement makes the circuits operated more efficient. The prototype circuit exhibits an INL of +0.3/-0.3 LSB and a DNL of +0.49/-0.49 LSB. The SNDR and SFDR achieve 31.3 and 49.2 dB at 1 GS/s for Nyquist input frequency. The ADC consumes 50 mW at 1.2V supply and occupies an active chip area of 0.16 mm2.ACKNOWLEDGMENT I ABSTRACT III TABLE OF CONTENTS Ⅴ LIST OF FIGURES Ⅶ LIST OF TABLES Ⅸ CHAPTER 1 INTRODUCTION 1 CHAPTER 2 FUNDAMENTALS OF ANALOG-TO-DIGITAL CONVERTER 2 2.1 PERFORMANCE METRICS 2 2.1.1 Signal-to-Noise Ratio (SNR) 2 2.1.2 Total Harmonic Distortion (THD) 2 2.1.3 Spurious-Free Dynamic Range (SFDR) 3 2.1.4 Signal-to-Noise and Distortion Ratio (SNDR) 3 2.1.5 Effective Number of Bits (ENOB) 3 2.1.6 Differential Nonlinearity (DNL) 4 2.1.7 Integral Nonlinearity (INL) 5 2.2 HIGH-SPEED AND LOW RESOLUTION ADC ARCHITECTURES 6 2.2.1 Two-step ADC 7 2.2.2 Full flash ADC 8 2.2.3 Folding and Interpolating ADC 9 CHAPTER 3 TIME-INTERLEAVED A/D CONVERTER 12 3.1 INTRODUCTION 12 3.2 TIME-INTERLEAVED A/D CONVERTER 12 3.3 CHANNEL MISMATCH EFFECTS 14 3.3.1 Offset mismatch effect 14 3.3.2 Gain mismatch effects 16 3.3.3 Clock timing error effects 17 3.3.4 Combined channel mismatch effects 18 CHAPTER 4 PROPOSED TIMING DIAGRAM AND FAST-SETTLING METHOD 21 4.1 CONVENTIONAL TWO-STEP ADC TIMING DIAGRAM 21 4.2 PROPOSED TIMING DIAGRAM 23 4.3 FAST-SETTLING METHOD 25 CHAPTER 5 CIRCUIT IMPLEMENTATION 29 5.1 ARCHITECTURE 29 5.2 MDAC 30 5.2.1 Residue of MDAC 32 5.3 OPERATIONAL AMPLIFIER 34 5.4 COMPARATOR 35 5.5 DIGITAL CIRCUIT FOR FAST-SETTLING 37 5.6 BIAS CIRCUIT AND CMFB CIRCUIT 38 5.7 CLOCK GENERATOR 39 5.8 SIMULATION RESULT 41 5.8.1 Operational amplifier simulation 41 5.8.1.1 AC analysis 41 5.8.1.2 Transient analysis 42 5.8.2 FFT test 43 5.8.3 Summary 44 CHAPTER 6 PERFORMANCE 45 6.1 FLOOR PLAN AND LAYOUT CONSIDERATIONS 45 6.2 TEST SETUP 48 6.3 PCB DESIGN 50 6.4 EXPERIMENT RESULT 54 6.4.1 Static performance 55 6.4.2 Dynamic performance 56 6.5 SUMMARY 59 CHAPTER 7 CONSLUSIONS 61 BIBLIOGRAPHY 623711023 bytesapplication/pdfen-US類比數位轉換器兩階段式時間交錯低功率ADCTwo-stepTime-interleavelow powerthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57374/1/ntu-96-R93943111-1.pdf