電機資訊學院: 電子工程學研究所指導教授: 黃俊郎李家安Lee, Chia-AnChia-AnLee2017-03-062018-07-102017-03-062018-07-102015http://ntur.lib.ntu.edu.tw//handle/246246/276565本論文提出一種能夠實作在現場可程式邏輯閘陣列 (FPGA) 之高面積效率與高解析度可編輯延遲電路結構，並且提出高面積效率的延遲元件，可使用這些延遲元件去組合成欲達成規格的可編輯延遲電路。相較於先前之研究，我們所提出的方法在面積效率上高五到二十五倍。然而，如果要量測全部的延遲值需要花太多時間，因此，為了節省量測時間，我們只量測部分的延遲值，用這些部分的延遲值去推測出全部的延遲值，並從當中選取我們想要的延遲值。我們使用實驗室虛擬儀器工程平台 (LabVIEW)開發程式去自動化量測延遲值，並且可以同時控制PXI FPGA Carrier與示波器。我們所開發出的可編輯延遲電路的結果，其解析度為50 ps、動態範圍為11.1 ns，功率消耗為1毫瓦特。In this work, the high area-efficient and high-resolution programmable delay line that can be implemented on FPGA is proposed. We also proposed high area-efficient delay cells based on FPGA architecture. Using the different characteristics of these delay cells to construct the desired programmable delay line. Compared to previous works, our method is 5 to 25 times more efficient in resource usage. However, it costs too much time to measure all delay values. To save time, we only measure partial delay values and use the proposed generation program to predict all delay values. Then, using the proposed selection program to select the desired delay values. To automatically measure delay values, we develop the LabVIEW program which can control the PXI FPGA Carrier and the oscilloscope at the same time. The measurement results show that the proposed programmable delay line achieves 50 ps resolution with 11.1 ns dynamic range. The power consumption is 1 mW.1848471 bytesapplication/pdf論文公開時間: 2020/8/16論文使用權限: 同意有償授權(權利金給回饋本人)可編輯延遲電路現場可程式邏輯閘陣列高面積效率高解析度programmable delay lineFPGAarea-efficienthigh resolutionthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/276565/1/ntu-104-R02943103-1.pdf