曹恆偉臺灣大學：電信工程學研究所趙國豪Chao, Kuo-HaoKuo-HaoChao2007-11-272018-07-052007-11-272018-07-052004http://ntur.lib.ntu.edu.tw//handle/246246/58682在較先進手機通訊標準中，調變信號的振幅並不是定值，所以對手機發射端的必v放大器來說，要對線性度和必v做出取捨。極座標發射機對於實現多傳輸標準和提升發射機必v有相當大的潛力。極座標發射機其中一主要部分為相位調變器。在我的研究中，建立了一套使用Simulink的相位調變器行為模型。評估極座標發射機的EVM、頻譜和對於相位和振幅信號不同步所造成的影響。最後使用一個三角積分調變除小數頻率合成器來實現部分相位調變器的射頻電路。其中相位頻率比較器、電流泵和多模數除頻器是用0.35μm混和信號CMOS製程的積體電路實現, 而三角積分調變器是用FPGA實現。In 2.5G or 3G communication system, the envelope of the modulation signal is non-constant, so it is a trade-off between the linearity and the efficiency of a power amplifier in the transmitter. Polar transmission techniques offer the capability of multi-standard and the potential for significant efficiency gains over solutions based on I/Q modulation. A main component of a polar transmitter is the phase modulator. In the work, we setup a complete behavior model of phase modulator in Simulink environment. The EVM and the power spectrum are estimated, and the effect of delay mismatch between the phase and envelope signal is also discussed. Finally, we use a Σ-Δ fractional-N frequency synthesizer to implement partial RF circuit of the phase modulator. A phase frequency detector, a charge pump and a multi-modulus divider are fabricated with 0.35μm 2p4m CMOS technology and are operated over 1 GHz. The Σ-Δ modulator is implemented by FPGA.Contents Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis overview 1 Chapter 2 Basic Concepts 3 2.1 Phase-Locked Loops 3 2.1.1 Basic Components 4 2.1.2 Linear Model of PLL 7 2.2 Frequency synthesizer 9 2.2.1 Direct Digital frequency synthesizer 9 2.2.2 PLL-based frequency synthesizer 10 2.3 Σ-Δ modulation 16 2.3.1 Quantization Noise of Σ-Δ Modulator 17 2.3.2 High Order Σ-Δ Modulator 19 2.3.3 Multi-stage Noise Shaped (MASH) Structure 20 2.4 Modeling of Fraction-N Frequency Synthesizer with Σ-Δ Modulator 21 2.5 Summary 24 Chapter 3 Polar transmitter 25 3.1 The modulation technique of EDGE 26 3.2 Review of traditional transmitter architecture 28 3.3 Polar transmitter architecture 30 3.3.1 Envelope modulator 31 3.3.2 Phase modulator 32 3.4 The challenge of polar transmitter 35 3.4.1 Wideband phase modulation 35 3.4.2 The Synchronization between Phase and Envelope Signal 36 3.5 Summary 38 Chapter 4 Behavioral Model 39 4.1 The word length of Phase Difference Signal 40 4.2 The Bandwidth of Phase Modulator 40 4.3 The Bandwidth of PLL 42 4.4 Frequency Resolution 44 4.5 Complete Model of Phase Modulator 46 4.6 Discussion of 3G systems 48 4.7 Summary 51 Chapter 5 Circuit Implementation 53 5.1 Phase Frequency Detector 54 5.2 Charge Pump 56 5.3 Frequency Divider 57 5.3.1 Dual-Modulus Prescaler Based Architecture 57 5.3.2 Programmable Prescaler Architectures 61 5.4 Loop Filter 66 5.5 PLL Implementation 67 5.6 Σ-Δ modulator 69 5.7 Compensation Filter 73 5.8 Class-E Power Amplifier 75 5.9 Summary 75 Chapter 6 Experiment Result 77 6.1 Testing setup 77 6.2 Integer-N mode measurement 78 6.3 Fractional-N mode measurement 80 6.4 Phase noise 81 6.5 Summary 81 Chapter 7 Conclusion 832662623 bytesapplication/pdfen-US極座標發射機鎖相迴路頻率合成器frequency synthesizerPLLpolar transmitterthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/58682/1/ntu-93-R91942039-1.pdf