2018-08-012024-05-17https://scholars.lib.ntu.edu.tw/handle/123456789/695707摘要：本計畫在開發應用於光積體電路系統中近紅外光波段傳輸之光電邏輯閘，將利用發光電晶體或電晶體雷射為光發射器及光接收器來製作光邏輯閘及光SR正反器儲存單元。執行規劃為三年，分三個階段，其中包含結構設計及模擬、電晶體製程及量測、參數萃取及模組化和光邏輯閘的電路設計及操作特性。首先，結構部分選用以InGaP/GaAs系統之異質接面雙極性電晶體並以InGaAs為主動區，使電晶體除了有原本的「電輸出」外還多了「光輸出」的雙輸出特性，此外，利用基極-集極的逆偏特性讓發光電晶體除了當光源外也可以作為光接收器。此階段將進行材料之磊晶校正，並進行製程研究與驗證，另一方面模擬結構折射率及光場，主要關鍵製程技術有兩項：(1)以水氧化方式進行電流及光場侷限，(2)利用乾蝕刻方式製作雷射共振腔鏡面。第二階段，將發光電晶體串接成基本光邏輯單元，例如：NOR閘、NAND閘等，利用外部光注入的方式，使開關調變速度達1Gb/s。第三階段，利用發光電晶體或電晶體雷射作為注入光源實現all-on-chip架構並將基本光邏輯單元串接成光SR正反器作為光基本儲存單元，並且有正確的時序操作。藉由此計畫可提升國內光通訊關鍵性元件與模組之競爭力及在國際上之能見度，因此本計畫之研究主題是相當具有創新學術、技術提昇。<br> Abstract: This project focuses on the development of near infrared comprehensive electrical/optical logic gate for optoelectronic integrated circuit. In this project, we will fabricate the light-emitting transistors (LETs) and the transistor lasers (TLs) which will be applied to optical transimitter, optical receiver, devices for optical logic gate and devices for optical SR latch as storage block to offer another “bit” operation than all tradidtional electrical gates or all optical gates. The three-year project is segmented into the following procedures including structure design, device simulation, device fabrication, device measurement, parameter extraction, modeling, layout design, characterization and analysis. The structure consists of InGaAs active region in the InGaP/GaAs heterojunction bipolar transistor (HBT). It allows the HBT as the unique “three-port” device (an electrical input, an electrical output, and a “third-port” optical output). With the tilted-charge minority carrier in the base region, the radiative recombination lifetime can be reduced to pico-second which enables LETs operating in gigahertz range. Futhermore, due to its reverse-biased base-collector junction, the LETs can not only operate as light sources but also photodetectors. The simultaneous photo-detection and amplification in one device, especially in the high speed optical communication systems, the large internal gain, low noise and compatibility with light emitters in epitaxial layer allow the possibility to realize high-performance cost-effective optoelectronic integrated circuits. In the first year, the epitaxyof the device will be verified and adjusted, and the fabrication process will be calibrated. Simultaneously, the refractive index calculation and the optical field simulation will be prepared. There are two key fabrication techniques must be considered: (1) utilize wet oxidation to achieve the current and optical confinement aperture, (2) the laser cavity mirror formation by ICP-RIE dry etch. In the second year, the basic optical logic gate like optical NOR, NAND gate will be demonstrated which is composed by a few LETs. The final goal is to achieve 1 Gb/s electrical/optical modualtion speed. In the third year, the all-on-chip operation by LET/TL will be realized. Moreover, the first optical SR latch will be demonstrated. This extra bit makes possible increase of capacity and reduction of cost. We believe the domestic optical communication industry will be stronger and have more inernational compititiveness in the global world by carrying out this project.發光電晶體電晶體雷射光邏輯閘Light-emitting transistortransistor laserOptical logic gate