Parallel architecture and hardware implementation of pre-processor and post-processor for sequence assembly

Kuo, Y.-H.Y.-H.KuoLiu, C.-S.C.-S.LiuLi, Y.-C.Y.-C.LiYI-CHANG LU2020-06-162020-06-162013https://scholars.lib.ntu.edu.tw/handle/123456789/502232[SDGs]SDG9Parallel architecture and hardware implementation of pre-processor and post-processor for sequence assemblyconference paper10.1109/ICASSP.2013.66378322-s2.0-84890498552https://www.scopus.com/inward/record.uri?eid=2-s2.0-84890498552&doi=10.1109%2fICASSP.2013.6637832&partnerID=40&md5=078af3dd2829d11e6ef4abd5cf3710a4