Yi-Chieh HuangPing-Ying WangSHEN-IUAN LIU2018-09-102018-09-102012-0315497747http://scholars.lib.ntu.edu.tw/handle/123456789/374056https://www.scopus.com/inward/record.uri?eid=2-s2.0-84862831781&doi=10.1109%2fTCSII.2012.2184378&partnerID=40&md5=0017a83f7d0ee9ce6b1421cd80813778An all-digital on-chip jitter tolerance measurement technique for clock/data recovery (CDR) circuits is presented. A 6-Gbps CDR circuit with this proposed technique is realized in a 90-nm CMOS process. The measured jitter tolerance by using the testing equipment and the proposed technique correlate within 13% in the frequency range of 178 kHz ∼ 11.3 MHz. The measured peak-to-peak data and clock jitters are 15.56 and 13.3 ps. The power of the CDR circuit is 44.4 mW at a supply voltage of 1.2 V. © 2006 IEEE.All-digital; clock and data recovery; jitter tolerance[SDGs]SDG7Clocks; Jitter; Timing circuits; All digital; Clock and data recovery; Clock jitters; Frequency ranges; Jitter tolerance; Measurement techniques; Supply voltages; Testing equipment; Clock and data recovery circuits (CDR circuits)journal article10.1109/TCSII.2012.21843782-s2.0-84862831781WOS:000302102400004