國立臺灣大學電機工程學系暨研究所闕志達2006-07-252018-07-062006-07-252018-07-061999-07-31http://ntur.lib.ntu.edu.tw//handle/246246/7712本計劃在於建立一適用於基頻訊 號處理單元設計之參數化模組庫與晶 胞庫。設計者設定參數於這些參數化 模組後，可直接進行功能階層模擬並 得到Verilog 閘階層硬體描述碼。藉由 這種設計方式我們可大幅縮短系統設 計時間並避免設計人員撰寫閘階層硬 體描述時可能發生的錯誤。我們提出 參數化模組類別及資料結構並據此實 作參數畫模組如各種邏輯晶胞陣列﹑ 加／乘法器與FIR 濾波器。在晶胞庫 設計部份，我們利用TSMC 0.6／ 0.35mm兩製程設計晶胞，兩晶胞庫各 提供56 種常用晶胞。我們調整電晶體 使其在低電壓可操作，並對不同狀況 下晶胞效能進行廣泛測試。The project is focused on developing the parametric module library and the standard cell libraries suitable for digital baseband signal processor design. The designers assign the parameters to parametric modules, perform function level simulations, and immediately get the corresponding gate-level Verilog code. With this design methodology we could drastically reduce the system design time and prevent errors made by designers. We purposed a parametric module class and several data structure. Based on these classes, we wrote a series of parametric modules including many kinds of logic arrays, high speed adders/multiplers, and FIR filters. The library cells are designed using TSMC 0.6/0.35mm technologies. Each standard cell library contains 56 frequently used cells. We sized the transistors in order to operate the cells in low-voltage conditions and finally performed an exhaustive test to garentee the cells meet the function/performance specifications.application/pdf920207 bytesapplication/pdfzh-TW國立臺灣大學電機工程學系暨研究所模組庫晶胞庫參數化模組module librarycell libraryparametric modulereporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/7712/1/882215E002039.pdf