陳秋麟臺灣大學：電子工程學研究所廖澤儒Ru, Liao - TzeLiao - TzeRu2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57391在商用的行動電子設備中，電池的續行力是個很重要的問題。現今的行動電話，個人數位助理，數位隨身聽等等。都期望有長時間的電池供應時間。因此電子裝置的功率效率越來越受到重視。 在許多的電子設備中，都有音訊的輸出裝置。傳統上的音訊輸出裝置是由A類輸出級，AB類輸出級或B類輸出級組成。但是傳統的輸出級體積大，功率效率低，而且容易發熱。因此，因應而生的D類輸出級便有了體積小，效率高等等的優點，可以更適用在現今的電子裝置中。 一般的使用D類輸出級之音頻放大器，都採用脈寬調變技術(Pulse Width Modulation)或是三角積分調變(Delta Sigma Modulation)技術。而該兩種調變方式的電路施行中，通常包含一個時脈電路。 本論文提出一使用三角積分器之D類放大器，並在三角積分器之電路施行方式中捨棄時脈電路，採用磁滯比較器取代量化器並得以節省下時脈電路，並仍可達到相當水準之輸出功率效率以及總協波失真。In the portable devices such as PDA, MP3 player or mobile phone and mobile amusement system, the battery life is a very important issue. In order to strengthen the battery lifetime, the high power efficiency will be better. The efficiency of power amplifier is very important. The traditional class A or class AB have lower efficiency than class D. The efficiency of class D will achieve 100% theoretically. The class D audio amplifier is usually with PWM modulator or delta sigma modulator to transform the input signal to a series of pulse signal to control the class D circuit. The traditional PWM modulator or delta sigma modulator are all with clock circuit inside. In order to reduce the clock circuit, a delta sigma modulator with hysteresis comparator is presented in this thesis. In this topology, we can save the chip area and also can achieve a good performance in THD and efficiency. The THD is 0.9% and the efficiency is 87% with 10K Hz input signal in this thesis.Chapter 1 Introduction ……………………………………………………1 1.1 Motivation …………………………………………………...1 1.2 Class D amplifier operation ……………………………………1 Chapter 2 Power amplifiers ………………………………………………5 2.1 Linear mode and switch mode power amplifier ………………5 2.2 Type of power amplifier …………………………………………6 2.2.1 Class A amplifier …………………………………………6 2.2.2 Class B amplifier …………………………………... 8 2.2.3 Class AB amplifier …………………………………..12 2.2.4 Class D amplifier ……………………………………….13 Chapter 3 Audio modulators ……………………………………………..16 3.1 PWM modulator ………………………………………………..16 3.2 Delta modulator ………………………………………………...19 3.3 Delta-sigma modulator …………………………………………24 Chapter 4 Circuit design and simulation………………………….29 4.1 Motivation ………………………………………………………29 4.2 System block diagram ………………………………………..29 4.3 Circuit implementation ………………………………………...36 4.3.1 Integrator ……………………………………………..36 4.3.2 Hysteresis comparator ……………………………..40 4.3.3 Class D amplifier …………………………………..45 4.3.4 Class D amplifier and Output filter …………………..47 4.3.5 Simulation results …………………………………..48 Chapter 5 Conclusions …………………………………………………..55 References ………………………………………………………………………..56546301 bytesapplication/pdfen-USD類放大器三角積分器Delta SigmaClass Dthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57391/1/ntu-95-R93943073-1.pdf