賴飛羆臺灣大學：資訊工程學研究所張四維Chang, Szu-WeiSzu-WeiChang2007-11-262018-07-052007-11-262018-07-052004http://ntur.lib.ntu.edu.tw//handle/246246/53774Dynamic power consumption goes down quadratically with the supply voltage scaling down. It is naturally for the researchers to scale down the supply voltage to reduce power consumption. It is also possible to reduce the power consumption in a design without degrading the performance by reducing the supply voltage of those cells o® the critical path. This method is so-called dual/multiple supply voltage methodology. However, it is also possible to provide dual/multiple threshold voltage to reduce the power consumption. As in [1] [2] [3] [4] [5] [6] [8] [7], many researches focus on assigning dual supply/threshold voltage to gate-level design. In this paper, we proposed a partitioning methodology with multiple supply voltage and multiple threshold voltage in behavioral synthesis stage. By considering multiple voltages and multiple thresholds in higher level of the design flow, we can explore larger design space of power, area, and performance. Hence we can optimize the power consumption without losing circuit e±ciency and area. And because the scheduling problem has been proven to be a NP problem, so we can not find optimal solution in polynomial time. To solve this, we adopt a GA (Genetic Algorithm) based SA (Simulated Annealing) approach to find an approximation result.Contents 1 Introduction 1 1.1 Low Power Requirement . . . . . . . . . . . . . . . . . . . . . 1 1.2 Power Dissipation of CMOS Circuit . . . . . . . . . . . . . . . 2 1.3 The E®ects in Deep Submicron Technology . . . . . . . . . . . 3 1.4 The General Synthesis Flow . . . . . . . . . . . . . . . . . . . 5 1.5 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Background 9 2.1 HLS Flow and Problems . . . . . . . . . . . . . . . . . . . . . 9 2.2 The Representation Methods of a System . . . . . . . . . . . . 11 2.3 Scheduling Problem and Some Basic Algorithms . . . . . . . . 13 2.4 GA (Genetic Algorithm) Overview . . . . . . . . . . . . . . . 16 2.4.1 The Typical Flow of GA in Algorithmic View . . . . . 17 2.4.2 GA Parameters . . . . . . . . . . . . . . . . . . . . . . 19 2.5 Simulated Annealing Overview . . . . . . . . . . . . . . . . . . 20 3 The GASA for Low Power Scheduling 22 3.1 The GA-Based SA Algorithm . . . . . . . . . . . . . . . . . . 23 3.2 Chromosome Representation . . . . . . . . . . . . . . . . . . . 25 3.3 GASA Operators and Parameters . . . . . . . . . . . . . . . . 29 3.4 Summary of Low-Power GASA Scheduling . . . . . . . . . . . 32 4 Experimental Results 33 4.1 Experiment Environment . . . . . . . . . . . . . . . . . . . . . 33 4.2 Experimental Results for Low-Power Dual Voltage Scheduling 35 4.3 Experimental Results for Low-Power Dual Voltage and Dual Threshold Voltage Scheduling . . . . . . . . . . . . . . . . . . 40 4.4 Discussion of Experimental Results . . . . . . . . . . . . . . . 44 5 Conclusion 472388910 bytesapplication/pdfen-US合成低功率排程GA-Based SAsynthesislowpowerthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53774/1/ntu-93-R91922050-1.pdf