Chen, Yi TingYi TingChenHuang, IanIanHuangLin, Min JuiMin JuiLinChuang, Shu YanShu YanChuangHo, Hua LingHua LingHoHsu, Kai SyangKai SyangHsuLin, Pin YuPin YuLinChen, Sih YingSih YingChenLIANG-HUNG LUSHIH-YUAN CHENJIUN-YUN LIJUN-CHAU CHIEN2023-10-172023-10-172023-01-0197983503476470149645Xhttps://scholars.lib.ntu.edu.tw/handle/123456789/636091This paper presents an on-wafer thru-reflect-series-resistance (TRS) VNA calibration in CMOS for device characterization at cryogenic temperatures. The algorithm resembles LRRM calibration while requiring only three calibration structures. The series-resistor standard is implemented using the polysilicon layer in the CMOS process, and its temperature dependency is characterized. We validate the calibration results using a 40-nm NMOS from DC-20 GHz using a cryogenic probe station down to 4K.calibration | cryogenic temperature | device modeling | LRRM | qubits | series resistance | TRL | vector network analyzerconference paper10.1109/IMS37964.2023.101880782-s2.0-85168559089https://api.elsevier.com/content/abstract/scopus_id/85168559089