Chen, P.P.ChenSHEN-IUAN LIUWu, J.J.Wu2020-06-112020-06-11200010577130https://scholars.lib.ntu.edu.tw/handle/123456789/499846https://www.scopus.com/inward/record.uri?eid=2-s2.0-0034270347&doi=10.1109%2f82.868466&partnerID=40&md5=6b6db30511baac9884315a9a5b28eda2A deep sub-nanosecond resolved CMOS pulse-shrinking delay element used in the time-to-digital converter (TDC) is proposed. The pulse-shrinking capability of the element is controlled by the dimension ratio of the adjacent gates. This control mechanism is completely different from the bias adjustment adopted in the conventional pulse-shrinking element. Without the need of continuous calibration, the presented element possesses not only extremely fine resolution, small single-shot errors, low power consumption, but also good insensitivity to the supply voltage variation. Being fabricated with 0.35-/Ltm CMOS technologies, the TDC made of the new elements has been measured to have a resolution of 68 ps. The effective resolution only varies 1.5 ps for a rather large supply voltage range from 3.5 to 4.5 V. The size of the circuit is 0.35 mm X 0.09 mm only, excluding the I/O pads. Under a single 3.3-V power supply, the static power dissipation, including the I/O pads, is 1 /LtW. The average power consumption is measured to be merely 1.2 mW under a measurement rate of 100 ksps. © 2000 IEEE.Delay line; Pulse-shrinking delay; TDC; Time interval measurementCMOS integrated circuits; Electric losses; Electric potential; Electric power supplies to apparatus; Electric power utilization; Integrated circuit manufacture; Time measurement; Pulse-shrinking delay elements; Electric delay linesjournal article10.1109/82.8684662-s2.0-0034270347