Ho, Tsung-YiTsung-YiHoSAO-JIE CHENYAO-WEN CHANG2020-06-162020-06-162004https://scholars.lib.ntu.edu.tw/handle/123456789/502018https://www.scopus.com/inward/record.uri?eid=2-s2.0-2942641881&doi=10.1145%2f981066.981074&partnerID=40&md5=d4dd8566fef83b0a38d799f2e9ecd2e8As technology advances into the nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using a built-in jumper insertion approach. Experimental results show that our approach reduced antenna-violated gates by about 98% and also achieved 100% routing completion for all circuits.Design for manufacturability (DFM); Multilevel optimization; Nanometer; Physical design; Process antenna effect; RoutingAntennas; Computer aided design; Gates (transistor); Integrated circuit layout; Microprocessor chips; Routers; Design for manufacturability (DFM); Physical design; Process antenna effects; Routing; VLSI circuitsconference paper10.1145/981066.9810742-s2.0-2942641881https://doi.org/10.1145/981066.981074