VLSI design of clustering analyser using systolic arrays

Dept. of Electr. Eng., National Taiwan Univ.Lai, M.F.M.F.LaiNakano, M.M.NakanoWu, Y.P.Y.P.WuHsieh, C.H.C.H.Hsieh2007-04-192018-07-062007-04-192018-07-061995-05N/Ahttp://ntur.lib.ntu.edu.tw//handle/246246/2007041910032504application/pdf512634 bytesapplication/pdfen-USVLSI design of clustering analyser using systolic arraysjournal articlehttp://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032504/1/00392513.pdf