A hierarchical analysis methodology for chip-level power delivery with realizable model reduction

Lee, Y.-M.Y.-M.LeeCHUNG-PING CHEN2020-06-112020-06-112003https://scholars.lib.ntu.edu.tw/handle/123456789/501008A hierarchical analysis methodology for chip-level power delivery with realizable model reductionconference paper10.1109/ASPDAC.2003.11950982-s2.0-84954455108https://www.scopus.com/inward/record.uri?eid=2-s2.0-84954455108&doi=10.1109%2fASPDAC.2003.1195098&partnerID=40&md5=19bd6839f7372a752bf4dcfd36657511