臺灣大學: 電信工程學研究所王暉廖信強Liao, Hsin-ChiangHsin-ChiangLiao2013-03-272018-07-052013-03-272018-07-052012http://ntur.lib.ntu.edu.tw//handle/246246/252581本論文涵蓋兩個研究方向，第一部分是針對在 V 頻帶之正交調變器 (I/Q modulator) 的設計分別提出被動元件的改良以及一個嶄新的方法來改善正交不匹 配性 (I/Q mismatch) 。而另一部份將探討有關在次毫米波 (sub-millimeter-wave) 功率放大器 (power amplifier) 之設計方法。 首先，第一部分呈現了一個實現於台積電 90 奈米金氧半場效電晶體 (CMOS) 製程之 V 頻帶寬頻正交調變器。為了改善於設計正交耦合器時所產生的正交不匹配性，我們使用了一個具有低振幅且相位不匹配以及對端點阻抗低敏感特性之共平面波導指叉式耦合器 (CPW interdigitated coupler) 。同時，藉由修改傳統馬遜式平衡與不平衡轉換器 (Marchand-type balun) 之接地平面結構，本地振盪源的漏流效應 (LO leakage) 也得到良好的抑制。另一個使用穩茂 0.15 微米假晶式高電子遷移率電晶體 (pHEMT) 製程之正交調變器引入了一個名為功率鎖定迴路 (power-locked loop) 系統之新穎的功率校正方法來達到寬頻的鏡像訊號抑制 (sideband suppression) 。此功率鎖定迴路系統運用了回授機制使正交不匹配性得以自動化調整，同時也克服了傳統耦合器在頻寬上的限制。上述兩個 V 頻帶之正交調變器分別呈現了大於 28 與 35 dBc 鏡像抑制率並擁用大於 17 GHz 的頻寬。此外，降低正交不匹配性對於整體系統向量強度錯誤率 (error vector magnitude, EVM) 的貢獻也經由高達 7 Gb/s 之高速傳輸實驗得到驗證。 此論文的第二部分闡述了一個異於傳統阻抗轉換的電路架構，並成功經由一個實現於台積電 65 奈米金氧半場效電晶體製程之 D 頻帶功率放大器驗證。作者於此提出的阻抗轉換網路可同時具備阻抗匹配以及功率結合的功能，並提供了多路功率結合的方法，目的在於提高整體輸出功率與提升效率。而多路功率結合產生的高阻抗傳換比在提出的阻抗轉換網路中也可解決，其結果可由大於 30 GHz 的小訊號頻寬來驗證。且因免除了額外的功率結合架構，此操作於 150 GHz 頻段之功率放大器於一小晶片面積內實現了大於 12 dBm 的飽和功率與 12% 的功率附加效率 (power-added efficiency, PAE)。This thesis is composed of two main researches. The first part is the investigations on two V-band I/Q modulators including the improvements on passive components and a creative method to enhance the I/Q balance, and the other part is the design topic about sub-millimeter-wave power amplifier. The first part starts with a V-band wideband I/Q modulator implemented in TSMC 90-nm CMOS process. In order to improve the I/Q mismatch in the design of quadrature phase, a co-planar waveguide (CPW) interdigitated coupler with low amplitude and phase imbalances and insusceptibility to port impedance is employed. The LO leakage is also effectively mitigated by revising the conventional Marchand-type baluns with incomplete ground plane. Another I/Q modulator fabricated in WIN’s 0.15-um pHEMT technology features wideband sideband suppression ratio with the novel power-level calibration method, power-locked loop system. A feedback mechanism is introduced to improve I/Q mismatch automatically and also overcomes the bandwidth restriction on conventional couplers. The two proposed I/Q modulators demonstrate lower than -28 and -35 dBc sideband suppression ratio, respectively, with wider than 17 GHz bandwidth. Moreover, the capability to minimize the I/Q mismatch contribution to system error vector magnitude (EVM) is verified by 7 Gb/s high speed transmission experiments. The second part presents the proposed impedance transformation network exemplified by a D-band power amplifier in TSMC 65-nm CMOS. In order to increase the output power and enhance the efficiency, the impedance transformation network integrates matching and power combining network simultaneously and also provides the solution of multi-ways power combining. The large impedance transformation ratio resulting from multi-way power combining can also be resolved in the procedure of proposed impedance transformation network. This can be verified by the small signal bandwidth of wider than 30 GHz. Furthermore, without additional power combining structures, higher than 12 dBm saturation power and 12 % power-added efficiency (PAE) are achieved with a compact chip size around 150 GHz.28217139 bytesapplication/pdfen-US正交調變器V頻帶共平面波導耦合器馬遜式平衡與不平衡轉換器功率鎖定迴路鏡像抑制高速傳輸功率放大器D頻帶阻抗轉換功率結合I/Q modulatorV-bandCPW couplerMarchand balunpower-locked loopsideband suppressionhigh speed transmissionpower amplifierD-bandimpedance transformationpower combiningthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/252581/1/ntu-101-R99942028-1.pdf