黃建璋Huang, JianJang臺灣大學:光電工程學研究所江宏禮Chiang, Hung-LiHung-LiChiang2010-07-012018-07-052010-07-012018-07-052009U0001-2807200914115700http://ntur.lib.ntu.edu.tw//handle/246246/188417近年來，金屬氧化物被人們廣泛研究，其中又以氧化鋅材料為主軸，其具有相當的可見光穿透率，高電子遷移率，並適合低溫製程等優點。氧化鋅薄膜電晶體被視為可撓性電路以及平面顯示器的新希望。但由應用於可撓性電路之氧化鋅電晶體受到低溫製程的影響，使得其穩定性降低。另一方面，其材料特性不同於傳統以單晶矽製作的電晶體，使得元件的分析窒礙難行。 在本篇論文中，我們在室溫下製作出高效能之氧化鋅薄膜電晶體。其操作電流高達1毫安培以上。同時我們針對常溫製程所面臨的問題加以討論，並且根據氧化鋅電晶體內部的物理機制，建立一個足以完整描述其電特性的元件模型。先，藉由觀察電特性較差的氧化鋅電晶體，我們發現其電容-電壓(Capacitance-Voltage, CV)曲線以及電流-閘極電壓(I-VG)曲線出現遲滯現象。同時，在電流-源極電壓(I-VDS) 曲線中，在飽和區間開始時，出現了過衝電流的現象。 對於I-VG中出現的遲滯現象，我們透過不同的偏壓方向、以及積分時間的準靜態CV量測，探討其絕緣層中的移動性離子電荷(mobile ionic charges)的影響，以解釋其特性曲線中的遲滯現象。 而針對飽和區開始時的過衝電流，我們透過晶界(grain boundary)物理模型加以解釋，並且經由X光繞射 (X-ray Diffraction)以及原子力顯微鏡(Atomic Force Microscopy)驗證氧化鋅薄膜的奈米晶體(nanocrystalline)之特性，取得晶粒大小。接著我們藉由射頻CV量測，以高低頻電容法求出其中的缺陷濃度，將上述實驗所得之參數放入模型當中進行模擬。最後，我們考慮電極之接觸電阻，以建立室溫下製作之氧化鋅薄膜電晶體之電路元件模型。Recently, metal-oxide materials have drawn a lot of attention in research field. ZnO is suitable for room-temperature process. It has lots of advantages such as high transparency in the visible light region, and high electron mobility. Thus ZnO is regarded as a potential material for flexible electronics and panel displays. However, due to the fabrication process at room temperature, ZnO-based devices have lower stability than Si-based transistors. Moreover, since the material property of ZnO is unique and different from Si, the analysis of ZnO-based devices is more difficult, compared with traditional transistors. In this work, we demonstrate high-performance ZnO-based thin film transistors fabricated at room temperature. The operating current is 1.4 mA at VGS = 6V and VDS = 20V. The Ion-Ioff ratio is higher than 1.0×106. We also make a discussion on the problems encountered in fabricating ZnO-based TFT at room temperature. And then based on the grain boundary theory, we build a model. With this model, we can completely describe the carriers transport mechanism in the channel layers of ZnO-based TFTs fabricated at room temperature. First of all, we analyze ZnO TFTs with poor electrical properties. Hysteresis can be observed from IDS-VG curves and C-V curves of these devices. We also find out overshoots in IDS-VDS curves. In the first part of this thesis, in order to explain the hysteresis observed from transfer curves, the C–V profiles are described by qausi-static capacitance-voltage (QSCV) measurement in deferent integration time and from different sweep directions. According to the measurement results, the hysteresis I-V curves and C-V curves is result from the mobile ionic charges in the insulating layer. In the second part of this thesis, we use a model based on the theory of grain boundary to explain overshoots observed in the I-VDS curves. We verify the nanocrystalline property of ZnO thin film by X-ray diffraction (XRD) pattern and atomic force microscopy (AFM) image. Meanwhile, we use the “high-low-frequency capacitance method” to calculate the trap density in the channel layer. Finally, using parameters from the experimental results, we demonstrate an analytical IDS-VDS model in this work.論文口試委員審定書誌要bstacthapter 1 Introduction 1hapter 2 Theory and Literatures Review 5.1 Thin Film Transistors 5.1.1 Metal-insulator-semiconductor capacitance 6.1.2 Oxide charges 12.1.3 Operation of thin film transistors 16.1.4 Si-based thin film transistors 18.1.5 Oxide-semiconductor-based thin film transistors 22.2 Properties of Materials 24.2.1 Zinc Oxide (ZnO) 24.2.2 Insulating materials 30.3 Sputtering 31.3.1 DC sputtering 31.3.2 RF magnetron sputtering 32hapter 3 Fabrication Process of ZnO TFTs and MIS Structures 37.1 Device Design 37.2 Hall Measurement of ZnO Thin Film 41.3 Quasi-static Capacitance Voltage Measurement 43hapter 4 Effects of Hysteresis and Trap-states on the Performance of ZnO TFT 47.1 Electrical Property and Different Sweep Direction 47.2 QSCV Characterization of ZnO MIS Structure 53.3 Nanocrystalline Model on the Grain Boundary 58.4 Simulation Result by Using the Nanocrystalline Model 64hapter 5 Conclusion 722112389 bytesapplication/pdfen-US氧化鋅薄膜電晶體電容-電壓奈米晶體元件模型zinc oxide (ZnO)thin film transistor (TFT)capacitance-voltage (CV)nanocrystalline,device modelthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/188417/1/ntu-98-R96941037-1.pdf