盧信嘉臺灣大學：電子工程學研究所黃韋超Huang, Wei-ChaoWei-ChaoHuang2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57312本篇論文主旨在於實現適用於IEEE 802.11a無線區域網路通訊系統之無線射頻功率放大器。此篇論文中，我們利用兩種不同方式來實現無線射頻功率放大器，第一種方式是將功率放大器整合於單一矽製程晶片中。第二種方式為利用覆晶技術和低溫共燒陶瓷製程將功率放大器整合成單一封裝並製成模組。 此篇論文中，我們採用相同的設計架構，不同的實現方式以比較其差異性。本研究利用全差動架構和電晶體自我偏壓方式來解決功率放大器在高功率輸出下會面臨的崩潰現象及熱載子效應，進而提升系統可靠度。 為了提高被動電路的品質因子與降低功率消耗，整合於單一封裝之功率放大器模組採用多層結構之低溫共燒陶瓷製程來實現外部匹配電路。利用此種多層結構來取代傳統平面印刷電路板的離散元件，將有助於未來達成系統封裝的理想。此外，為了使功率放大器可與中頻，基頻電路做整合，本研究採用台積電0.18-μm製程提供之標準射頻電晶體模型且供給電壓定於1.8伏特。The purpose of this thesis is to present a power amplifier which can be used in IEEE 802.11a WLAN system. In this thesis, the power amplifier is implemented by two approaches, one uses fully on-chip integrated technique and another uses LTCC on-package integrated and flip-chip connection techniques. In order to investigate the difference between on-chip integrated PA and on-package integrated PA, these two amplifiers are built with the same topology. We adopt differential self-biased cascode topology to overcome the problems of hot carrier effect and break down effect when the power amplifier is operating in 23.2 dBm high output power. Accordingly, the differential self-biased cascode topology can improve the reliability of power amplifier significantly. Three-stage architecture is chosen in these power amplifiers for more than 20 dB high gain at 5 GHz. The passive part of on-package integrated PA is implemented by low temperature co-fired ceramic (LTCC), with inherently high quality factor, can improve the efficiency drastically. The replacement of PCB discrete passive components by multilayer LTCC embedded one makes the concept of system-on-a-package (SOP) real. Furthermore, the implementation of power amplifier with TSMC 0.18-μm CMOS process and 1.8 V DC supply voltage make it possible to integrate the IF and base-band circuits in a single chip.Table of contents Chapter 1 1 Introduction 1 1.1 Previous art 1 1.2 WLAN communication architecture 3 1.3 SOC and SOP in wireless communication 4 1.4 Motivation 6 1.5 Literature review 7 1.6 Overview 9 Chapter 2 11 IEEE 802.11a WLAN Communication System Specification for Power Amplifier 11 2.1 IEEE 802.11a system specification 11 2.2 IEEE 802.11a channel allocation 13 2.3 Transmit spectral mask and receiver sensitivity 14 2.4 Introduction to orthogonal frequency division multiplexing (OFDM) 16 2.5 Basic concepts in RF design 18 2.5.1 Definition of power gain 18 2.5.2 1-dB compression point 18 2.5.3 Third-order interception point 20 2.5.4 Stability factor 23 2.5.5 Error Vector Magnitude 25 Chapter 3 27 Design of a Fully On-Chip Integrated Differential CMOS Power Amplifier 27 3.1 Previous art 27 3.2 Introduction to linear power amplifier 28 3.3 Submicron CMOS PA design constrains 33 3.3.1 Conventional cascode topology 34 3.3.2 Self-biased cascode topology 36 3.4 Power device size selection 38 3.4.1 Load line analysis 38 3.4.2 Load pull impedance simulation 39 3.5 Fully integrated differential CMOS power amplifier design 40 3.5.1 Power amplifier schematic architecture 40 3.5.2 Driver stage architecture 41 3.5.3 Power stage architecture 42 3.5.4 Physical layout and EM simulation 43 3.6 Simulation result of CMOS PA 46 3.6.1 Scattering parameters 46 3.6.2 Stability factor analysis 47 3.6.3 Third-order intercept point 49 3.6.4 AM-to-PM distortion simulation 50 3.6.5 Large signal simulation result 51 3.6.6 Transmit spectral mask and EVM simulation 52 Chapter 4 53 Design of a Fully Differential RF-SOP PA Using Flip-Chip and LTCC Process 53 4.1 Introduction 53 4.2 Low temperature co-fired ceramics 54 4.2.1 LTCC fabrication process 54 4.2.2 Material used in LTCC 57 4.2.3 Advantage of LTCC process 57 4.3 Flip-chip technology 58 4.3.1 Traditional wire bond method 59 4.3.2 Advantages of flip-chip technology 61 4.4 Differential RF-SOP PA design using flip-chip and LTCC process 63 4.4.1 Why integrated in LTCC? 63 4.4.2 Why flip-chip connection? 64 4.4.3 Schematic diagram of differential RF-SOP PA 66 4.4.4 LTCC passives design 68 4.5 Co-simulation result of RF-SOP PA 71 4.5.1 Co-simulated scattering parameters 71 4.5.2 Co-simulated stability factor analysis 72 4.5.3 Third-order intercept point 74 4.5.4 LTCC process variation test 75 4.5.5 Large signal co-simulation result 76 4.5.6 Transmit spectral mask and EVM simulation 77 4.6 Performance comparison between fully on-chip and RF-SOP PA 78 Chapter 5 79 Measurement Procedures and Current Result 79 5.1 Measurement procedures of on-chip PA 79 5.1.1 On-chip PA small signal S-parameter test setup 79 5.1.2 On-chip PA large signal measurement setup 83 5.2 The 5-GHz 180˚ coupler 86 5.3 Measurement procedures of RF-SOP PA 88 5.3.1 Small signal measurement setup for RF-SOP PA 88 5.3.2 Large signal measurement setup for RF-SOP PA 89 5.4 Currently measurement results 92 Chapter 6 95 Conclusion 95 Reference 98 List of Figures Fig. 1.1 Simplified dual-band tri-mode 802.11a/b/g chipset block diagram [6]. 3 Fig. 1.2 Cost comparison of LTCC vs. FR4 [8]. 5 Fig. 2.1 Multi pass phenomenon and its effect on transmission channel [59]. 12 Fig. 2.2 Channel allocation of IEEE 802.11a standard within the UNII band. 13 Fig. 2.3 Transmit spectrum mask of 802.11a 15 Fig. 2.4 Modulation diagram of OFDM signal. 17 Fig. 2.5 8-subcarrier OFDM signal 17 Fig. 2.6 Definition of 1-dB compression point. 19 Fig. 2.7 Intermodulation in a nonlinear system. 20 Fig. 2.8 Growth of output power in an intermodulation test. 22 Fig. 2.9 Schematic for 2-port gain and stability analysis [1]. 23 Fig. 2.10 Graphically representation of error vector magnitude [61]. 25 Fig. 3.1 Reduced conduction angle current waveform. 28 Fig. 3.2 Class A, B, AB and C bias points on DC-IV curve. 29 Fig. 3.3 Fourier analysis of reduced conduction angle mode. 31 Fig. 3.4 RF power and efficiency as a function of conduction angle. 32 Fig. 3.5 Conventional cascode amplifier. 35 Fig. 3.6 Voltage waveforms versus time. 35 Fig. 3.7 Self-biased cascode amplifier. 37 Fig. 3.8 Voltage waveform versus time in self-biased cascode amplifier. 37 Fig. 3.9 Self-biased topology and single transistor DC-IV curve comparison. 37 Fig. 3.10 Load line analysis. 39 Fig. 3.11 Load pull impedance simulation. 39 Fig. 3.12 Simplified schematic of designed differential three-stage PA. 41 Fig. 3.13 The single end half circuit of driver stages. 42 Fig. 3.14 Differential output power stage schematic diagram. 42 Fig. 3.15 The three-stage differential PA Layout. 43 Fig. 3.16 Layout post simulation by EM simulator. Metal lines in circles in the (a) driver stage and (b) power stage are modeled by EM simulator. (c) 3D structure of stacked power metal line. 45 Fig. 3.17 Simulated scattering parameters of (a) S11, S22 and (b) S21 and maximum available gain (MAG) 47 Fig. 3.18 (a) Simulated k-factor from DC to 60 GHz. (b) inter-stage stability circle. 49 Fig. 3.19 Two-tone test for IP3 and IM3 50 Fig. 3.20 The AM-to-PM distortion 51 Fig. 3.21 Large signal simulation result 51 Fig. 3.22 Output spectrum and signal constellation at POUT = 16.3 dBm. 52 Fig. 4.1 Procedures of making the tape. 55 Fig. 4.2 Low-temperature co-fired ceramics manufacturing process. 56 Fig. 4.3 Multiple-chip module integrated in SIP format 58 Fig. 4.4 The filp-chip approach: mounting a flipped chip onto a motherboard using bump interconnects. 59 Fig. 4.5 Die attachment by wire bond method and flip chip technology [41]. 60 Fig. 4.6 Heat sinking through the motherboard and electrical grounding using a via array [57]. 62 Fig. 4.7 Simplified schematic of fully differential three-stage RF-SOP PA 66 Fig. 4.8 (a) Physical layout of RF-SOP PA and (b) flip-chip structure. 67 Fig. 4.9 The 2-D view of (a) versionⅠand (b) versionⅡLTCC passive design. 69 Fig. 4.10 The 3-D view of (a) version Ⅰ and (b) version Ⅱ RF-SOP PA. 70 Fig. 4.11 Co-simulated scattering parameters of (a) S11, S22 and (b) S21, maximum available gain (MAG). 72 Fig. 4.12 Co-simulated (a) k-factor and (b) inter-stage stability circle. 74 Fig. 4.13 Two-tone test for OIP3 and IM3 75 Fig. 4.14 Small signal S-parameter simulation of LTCC process variation 75 Fig. 4.15 Large signal simulation result. 76 Fig. 4.16 Output spectral and signal constellation at POUT = 17.1 dBm. 77 Fig. 5.1 Microphotograph of (a) fully differential on-chip integrated PA and (b) its floor plan. 80 Fig. 5.2 The used 100-μm pitch differential RF probe. 81 Fig. 5.3 (a) On-wafer probing for small signal test. (b) On wafer probing for small signal and wire bonding for DC. (c) On wafer probing for DC and RF signal by using flip-chip technique. 82 Fig. 5.4 Large signal measurement setup. 84 Fig. 5.5 Two-tone test for OIP3 measurement 84 Fig. 5.6 Output IP3 calculation. 85 Fig. 5.7 802.11a modulated signal measurement setup for power amplifier. 85 Fig. 5.8 The 5-GHz 180˚ coupler implemented by PCB. 86 Fig. 5.9 The measured S-parameters of the 180˚ coupler. 87 Fig. 5.10 The measured phase difference between port (1, 3) and port (2, 3). 87 Fig. 5.11 Top view of RF-SOP PA and its floor plan. 88 Fig. 5.12 Small signal measurement setup for RF-SOP PA. 89 Fig. 5.13 Large signal measurement setup for RF-SOP PA 90 Fig. 5.14 Two-tone test for OIP3 measurement. 90 Fig. 5.15 802.11a modulated signal test for RF-SOP PA. 91 Fig. 5.16 (a) On-chip PA small signal measurement setup, (b), (c), (d) simulated and measured scattering parameter comparison. 93 List of tables Table 1.1 Wireless LAN standards summary 7 Table 1.2 Summary of recently published WLAN power amplifier. 8 Table 1.3 Summary of currently available commercial products. 8 Table 2.1 The specification of the receiver sensitivity and adjacent channel rejection with data rate from 6 to 54 Mbps. 15 Table 4.1 RF performance summary of fully on-chip and RF-SOP PA. 78 Table 6.1 Comparison table of recently published WLAN power amplifiers. 96 Table 6.2 Summary of currently available commercial products. 975349672 bytesapplication/pdfen-US功率放大器差動式低溫共燒陶瓷覆晶cmos power amplifierflip-chipLTCCWLANthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57312/1/ntu-95-R93943087-1.pdf