Chou, Ang ShengAng ShengChouHsu, Ching HaoChing HaoHsuLin, Yu TungYu TungLinArutchelvan, GouthamGouthamArutchelvanChen, EdwardEdwardChenHung, Terry Y.T.Terry Y.T.HungHsu, Chen FengChen FengHsuChou, Sui AnSui AnChouLee, Tsung EnTsung EnLeeMadia, OresteOresteMadiaDoornbos, GerbenGerbenDoornbosSu, Yuan ChunYuan ChunSuAzizi, AminAminAziziSathaiya, D. MahaveerD. MahaveerSathaiyaCai, JinJinCaiWang, Jer FuJer FuWangChung, Yun YanYun YanChungWu, Wen ChiaWen ChiaWuNeilson, KatieKatieNeilsonYun, Wei ShengWei ShengYunHsu, Yu WeiYu WeiHsuHsu, Ming ChunMing ChunHsuHou, Fa RongFa RongHouShen, Yun YangYun YangShenChien, Chao HsinChao HsinChienWu, Chung ChengChung ChengWuWu, JeffJeffWuWong, H. S.PhilipH. S.PhilipWongChang, Wen HaoWen HaoChangVan Dal, MarkMarkVan DalCheng, Chao ChingChao ChingChengCHIH-I WURadu, Iuliana P.Iuliana P.Radu2024-03-132024-03-132023-01-01979835032767001631918https://scholars.lib.ntu.edu.tw/handle/123456789/640830Two-dimensional (2D) transition metal dichalcogenide (TMD) materials are regarded as promising channel candidates for extreme contacted gate pitch (CGP) scaling. However, basic demonstration of the modules required to build logic devices is limited. For the first time, we demonstrate comparable n-type and p-type high-performance on 2D transistors. Translation to 300 mm wafer processing is tested by die-by-die transfer of the 2D material. The 300 mm fabrication preserves a relatively high mobility of 30 cm2/V•s. We demonstrate scaling of nMOS contact length (LC) to 12 nm and top gate length (LG) to 10 nm. Devices maintain high current density at short LC as well as in top-gate only operation.Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channelconference paper10.1109/IEDM45741.2023.104137792-s2.0-85185573058https://api.elsevier.com/content/abstract/scopus_id/85185573058