顧孟愷臺灣大學：資訊工程學研究所蔡德政Tsai, Der-TzengDer-TzengTsai2007-11-262018-07-052007-11-262018-07-052007http://ntur.lib.ntu.edu.tw//handle/246246/53951Networks-on-chip (NOC) has been proposed as a promising solution to complex on-chip communication problem. It is used to overcome the communication and the performance bottlenecks of bus based interconnection. NOC architecture consists of a collection of intellectual property (IP) cores interconnected by on-chip routers. Since an application-specific NOC for one SOC design can not be re-applied to another SOC design, it is essential to devise a tool for generating fast and efficient NOC. In this work, we propose a tool that generates application-specific networks-on-chip automatically by giving application description files and connection files. We also design the components of NOC including routers and network interfaces. We focus on a mesh-based topology and packet switching NOC. We present a fast algorithm for mapping cores onto a mesh-based NOC, minimizing the communication delay. Compared with other work, simulation results with two benchmarks make significant savings on communication cost by using our tool. This tool is applied to AES-RS codec and LDPC decoder. All results are verified on Alter'a FPGAs.Contents 1 Introduction 1 1.1IntroductiontoHardwareSoftwareCo-designandSystem-on- a-Chip...............................1 1.2 Networks-on-ChipandAutomationToolIntroduction.....3 1.3 Motivation.............................5 1.4 ThesisOrganization........................6 2 Networks on Chip Architecture 8 2.1 OurNetworksonChipArchitectureOverview.........9 2.1.1 Topology..........................10 2.1.2 CommunicationModel..................11 2.1.3 Switching.........................12 2.1.4 RoutingandPacketFormat...............12 2.1.5 FlowControl,Bu?eringandArbitration........15 2.1.6 RouterArchitecture...................15 2.2 RelatedWorks...........................19 3 NOC AUTOMATION DESIGN FLOW 23 3.1 NetworkInterfaceArchitecture.................23 3.2 TheDesignofNetworksonChipGenerationandIPMapping Tool................................24 3.2.1 parametricNOCtopologygeneration..........25 3.2.2 communicationcostconstrainedIPmappingmethod.26 3.2.3 IPdescriptionfile.....................29 3.2.4 connectionfile.......................31 3.2.5 IPmappingresultfile...................31 3.2.6 NOCareareduction...................35 4 CASE STUDY AND EXPERIMENTAL RESULTS 36 4.1 simulationresult.........................36 4.2 FPGAimplementation:casestudy...............38 4.2.1 ourdevelopmentenvironment..............38 4.2.2 Case1:AESandRScodec................39 4.2.3 LDPCdecoder......................44 5 CONCLUSION AND FUTURE WORK 48 5.1 Conclusion.............................48 5.2 FutureWork............................491066895 bytesapplication/pdfen-US系統晶片網路晶片網路介面SOCNOCnetwork interfacethesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53951/1/ntu-96-R94922101-1.pdf