王勝德臺灣大學：電機工程學研究所許家祥Hsu, Chia-HsiangChia-HsiangHsu2007-11-262018-07-062007-11-262018-07-062006http://ntur.lib.ntu.edu.tw//handle/246246/53347We examine the possible energy savings by mapping critical software functions from a microprocessor to configurable logics. A system-on-a-chip containing configurable logic is now commercially available. The configurable logic is typically intended to implement peripherals and co-processors without increasing chip count. We show that reduced software energy is an extra significant benefit, making such chips even more useful. We identify critical software functions of an application and implement them in the configurable logic such that the application can complete sooner, allowing us to put the system in a low-power state for longer periods, thus reducing energy. We use estimation-based approach for a hypothetical device having a 32-bit MIPS-extension processor plus on-chip configurable logic, yielding energy savings of 40%, increasing to 54% assuming voltage scaling.1 Introduction 1 1.1 Preliminary . . . . . . . . . . . . . . . . . . . . . 1 1.2 Related Work . . . . . . . . . . . . . . . . . . . . 5 1.3 Summary . . . . . . . . . . . . . . . . . . . . . . . 7 2 Power Estimation Model 8 2.1 Internal Energy . . . . . . . . . . . . . . . . . . . 9 2.1.1 Software Microprocessor Power Estimation . . . . . 9 2.1.2 Hardware Co-Processor Power Estimation . . . . . . 10 2.2 External Energy . . . . . . . . . . . . . . . . . . .10 2.3 Dynamic Voltage Scaling . . . . . . . . . . . . . . .12 2.3.1 DVS Technology Requisites and Basic Concept . . . .13 2.3.2 Previous work . . . . . . . . . . . . . . . . . . .14 2.3.3 Dynamic Voltage Scaling in Hardware/Software Parti- tioning . . . . . . . . . . . . . . . . . . . . . . . . .16 2.4 Summary . . . . . . . . . . . . . . . . . . . . . . .17 3 Partitioning Approach 18 3.1 Problem Description . . . . . . . . . . . . . . . . .18 3.2 Traditional Source-Based Approach . . . . . . . . . .19 3.3 Procedural Functional Partitioning . . . . . . . . . 19 3.3.1 Reduced Power . . . . . . . . . . . . . . . . . . .21 3.3.2 Reduced Time . . . . . . . . . . . . . . . . . . . 21 3.4 Summary . . . . . . . . . . . . . . . . . . . . . . .22 4 Experiments and Results 23 4.1 Profiling with GNU Tools . . . . . . . . . . . . . . 23 4.2 Estimation-Based Power and Performance Evaluation . .25 4.2.1 To Determine Software Cycles and Power . . . . . . 25 4.2.2 To Determine Hardware Cycles and Power . . . . . . 26 4.2.3 Total System Energy . . . . . . . . . . . . . . . .27 4.3 Results . . . . . . . . . . . . . . . . . . . . . . .28 4.4 Potential Results with Voltage Scaling . . . . . . . 30 4.5 Summary . . . . . . . . . . . . . . . . . . . . . . .31 5 Conclusions 3214005764 bytesapplication/pdfen-US電源消耗軟/硬體劃分電壓調整energy consumptionhardware/software partitioningvoltage scaling[SDGs]SDG7thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53347/1/ntu-95-R93921105-1.pdf