陳少傑臺灣大學：電子工程學研究所張祐維Chang, You-WeiYou-WeiChang2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57300近年來，隨著半導體技術和製程的成長與進步，無線通訊的發展日趨成熟，已逐漸取代傳統有線通訊的地位。過去在無線通訊上所面臨的瓶頸，已經獲得越來越多的解決方法。 我們實驗室的研究目標為以零中頻的架構設計出符合IEEE 802.11b標準的無線區域網路收發機，其中包含前端接收器、通道選擇濾波器、可調式增益放大器和鎖相迴路。本篇論文著重在如何設計及實作前端接收器的部份，包含低雜訊放大器、Gilbert cell 的混波器、除頻器及驅動的緩衝器。在設計實作中均有考慮靜電防護措施，包裝的模型和傳輸線的效應。 本次實作使用台灣積體電路公司CMOS 0.25μm的製程，其中我們著重於零中頻架構所會面臨到的問題及其解決辦法，整個電路均採用單一晶片的設計，並以小面積及低必v消耗為設計考量。 電路設計所採用的供應電壓為2.7V。模擬結果如下:低雜訊放大器在高增益狀態下的增益為27.2dB、具3.49dB 的雜訊指數和-18dBm的輸入三階交叉點。在低增益狀態下有 3.5dB的增益、13.8dB的雜訊指數和7.2dBm的輸入三階交叉點。混波器則有 6.4dB的增益、19.8dB 的雜訊指數和2.8dBm的輸入三階交叉點。 除頻器提供頻率為2.4GHz，大小為-4dBm的訊號給混波器的在地端。In recent years, with the growth of semiconductor process and technology, the wireless communication replaces the wired system gradually. More and more solutions are developed toward low power and high integration. The target of our laboratory research is to design an 802.11b WLAN transceiver by using zero-IF architecture. We divide the transceiver into several parts: Front-End Receiver, Channel Select Filter, Variable Gain Amplifier and Phase Lock Loop. This Thesis is focused on the design flow and implementation of a front-end receiver. The building blocks include a Low Noise Amplifier (LNA), two modified Gilbert cell mixers, and a divider with driving buffers. The Electro-Static-Discharge (ESD) protection circuit, package model, and transmission line effect have all been considered in the design process. We use the TSMC CMOS 0.25μm process technology. We stress on the solution of zero-IF architecture for IEEE 802.11b. The whole circuit used on-chip inductors and achieved a small size and low power design. The power supply is 2.7V. The simulation results of the proposed LNA are 25.4dB gain, 3.5dB noise figure, -18dBm IIP3, and -27dBm P1-dB at the high-gain mode. In the low-gain mode, the performances are 1.8dB gain, 13.8dB noise figure, 7.2dBm IIP3 and -5dBm P1-dB. The simulation results of the mixer are 6.4dB gain, 19.8dB noise figure, 2.8dBm IIP3 and -6.2dBm P1-dB. The divider with driving buffers provide -4dBm LO signal at 2.4GHz.ABSTRACT ………………………………………………………………………… i LIST OF FIGURES ……………………………………………………………… vi LIST OF TABLES …………………………………………………………………… ix CHAPTER 1. INTRODUCTION …………………………………………………… 1 1.1 Background and Motivation ………………………………………… 1 1.2 Thesis Outline ………………………………………………………… 2 CHAPTER 2. REVIEW OF RECEIVER ARCHITECHTURES …………………… 5 2.1 Receiver Architecture s ……………………………………………… 5 2.1.1 Heterodyne Receiver ………………………………………… 5 2.1.2 Zero-IF Receiver ……………………………………………… 8 2.1.3 Low-IF Receiver ……………………………………………… 11 2.1.4 Our Choice …………………………………………………… 12 2.2 General Consideration in LNA ………………………………………… 14 2.2.1 Conversion Gain ……………………………………………… 14 2.2.2 Noise Figure ……………………………………………… 14 2.2.3 Linearity …………………………………………………… 15 2.3 General Consideration of Mixer …………………………………… 17 2.3.1 Conversion Gain ……………………………………………… 18 2.3.2 Noise Figure ……………………………………………… 18 2.3.3 Port to Port Isolation ………………………………………… 19 2.3.4 Linearity …………………………………………………… 19 2.4 Divider with Driving Buffer ………………………………………… 20 2.4.1 Bandwidth …………………………………………………… 20 2.4.2 Phase Imbalances ………………………………………… 21 CHAPTER 3. DESIGN AND IMPLEMENTATION OF A 2.4GHZ RECEIVER …… 23 3.1 Specification Budget Analysis ………………………………………… 23 3.2 LNA …………………………………………………………………… 25 3.2.1 Motivation …………………………………………………… 26 3.2.2 LNA Topology ……………………………………………… 27 3.2.3 LNA Simulation Results …………………………………… 29 3.2.4 LNA Simulation Results Summary…………………………… 34 3.3 Mixer …………………………………………………………………… 35 3.3.1 Motivation …………………………………………………… 35 3.3.2 Mixer Topology ……………………………………………… 36 3.3.3 Mixer Simulation Results …………………………………… 40 3.3.4 Mixer Simulation Results Summary ………………………… 44 3.4 Divider with Driving Buffer ………………………………………… 44 3.4.1 Motivation …………………………………………………… 44 3.4.2 Divider with Driving Buffer Topology …………………… 45 3.4.3 Divider and Buffer Simulation Results …………………… 50 3.4.4 Divider and Buffer Simulation Results Summary ………… 52 3.5 Receiver Front-End Simulations …………………………………… 53 3.5.1 Simulation Results of Conversion Gain and Noise Figure …… 53 3.5.2 Simulation Result of P1-dB Gain Compression ……………… 54 3.5.3 Simulation Results of IIP3 …………………………………… 55 3.5.4 Summary of Simulation Results ……………………………… 57 CHAPTER 4. IMPLEMENTATION AND MEASUREMWNT …………………… 59 4.1 LNA Testkey ………………………………………………………… 59 4.1.1 Measurement Results ………………………………………… 61 4.1.2 Measurement Summary of LNA Testkey …………………… 64 4.2 Implementation ………………………………………………………… 64 4.3 Summary ……………………………………………………………… 67 CHAPTER 5. CONCLUSION AND FUTURE WORK ………………………… 69 5.1 Conclusion ……………………………………………………………… 69 5.2 Future Work ………………………………………………………… 69 REFERENCES …………………………………………………………………… 713490516 bytesapplication/pdfen-US混波器低雜訊放大器無線區域網路Wireless LANMixer802.11bLNAthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57300/1/ntu-93-R91943061-1.pdf