國立臺灣大學電子工程學研究所陳中平2006-07-262018-07-102006-07-262018-07-102004-10-31http://ntur.lib.ntu.edu.tw//handle/246246/20028Due to coupling noises, process avariations, and power delivery fluctuations, design uncertainties of on-chip global interconnect systems rise sharply with deep-sub-micron (DSM) technology. It is increasingly difficult to assume deterministic and error-free signal transmission over global wires. Instead, on-chip global interconnect wires must be analyzed as an errorprone communication channel characterized by probability of bit error, and statistical timing distributions. In this paper, a novel statistical timing analysis approach is developed to analyze the behavior of two practically important pipelined multiple clock-cycle global interconnect architectures, namely, the flipflop inserted global wire and the latch inserted global wire. We present analytical formula that are based on parameters obtained using Monto Carlo simulation. These results enable a global interconnect designer to explore design trade-offs between clock frequency and probabilty of bit-error during data transmission, and to evaluate cost-effectiveness of reliability enhancement measures such as bus coding.application/pdf103124 bytesapplication/pdfzh-TW國立臺灣大學電子工程學研究所reporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/20028/1/922220E002019.pdf