Tai, H.-Y.H.-Y.TaiTsai, P.-Y.P.-Y.TsaiTsai, C.-H.C.-H.TsaiHSIN-SHU CHEN2018-09-102018-09-102013https://www.scopus.com/inward/record.uri?eid=2-s2.0-84893529933&doi=10.1109%2fASSCC.2013.6691036&partnerID=40&md5=a951dff6011306b39555b44cc326414bhttp://scholars.lib.ntu.edu.tw/handle/123456789/379866A 6-bit 1.25GS/s single-channel asynchronous SAR ADC skipping the comparator metastability is presented. A delay-shift technique is proposed to shift the comparator delay to generate the 1.5-bit redundancy range and to accelerate the comparison speed. It compensates the dynamic offset by the redundancy. This ADC in 40nm CMOS technology achieves 37.1dB peak SNDR and consumes 5.3mW at 1.2V supply. It results in an FoM of 73fJ/conversion-step. Due to no extra calibration circuit, the core circuit only occupies an area of 0.004mm2. © 2013 IEEE.Analog to digital converter (ADC); Metastability; Redundancy; Successive approximation register (SAR)40nm cmos; Analog to digital converters; Calibration circuits; Core circuit; Metastabilities; SAR ADC; Single-channel; Successive approximation register; Analog to digital conversion; CMOS integrated circuits; Comparators (optical); Redundancyconference paper10.1109/ASSCC.2013.66910362-s2.0-84893529933