劉深淵臺灣大學：電子工程學研究所范哲瑋Fan, Che-WeiChe-WeiFan2007-11-272018-07-102007-11-272018-07-102007http://ntur.lib.ntu.edu.tw//handle/246246/57227近年來，無線通訊在資料傳輸上都一直扮演著相當重要的角色。超寬頻系統在下一代行動通訊上，被定位為短距離(10m)、高傳輸速率(480Mb/s)、低功率消耗的規格。多頻帶 OFDM 聯盟(MBOA)所提出的多頻帶正交頻率多工(MB-OFDM)規格似乎是目前所主要被採用。然而，在多頻帶正交頻率多工超寬頻(MB-OFDM UWB)系統中最難被實現的一部份就是頻率合成器。 雖然多頻帶 OFDM 聯盟把 3GHz到 10GHz分成 14個 528MHz頻寬的次頻帶，但其中頻帶1-3所組成的模組1還是最有市場經濟價值。儘管文獻已有不同作法，單邊頻混頻(SSB mixing)架構仍是最被常使用。在此論文中，我們提出不同單邊頻混頻架構以實現多頻帶正交頻率多工超寬頻系統模組1之頻率合成器。同時為了達到高度系統整合以及低成本需要，我們採用CMOS製程來實現。 我們提出了以單一鎖相迴路為基礎的頻率合成器架構來減少多組鎖相迴路的使用，藉由這個方式可以大幅減少被迴路濾波器所占的晶片面積，並且使用耦合壓控振盪器以及耦合注入鎖定除頻器技巧可以降低其功率消耗。利用0.18微米CMOS製程實現的頻率合成器消耗 65 毫瓦，在內頻帶突刺(in-band spur)上有著 -36dBc 的表現。在0.13微米CMOS製程實現的頻率合成器中，我們更加提出一個具電流循環利用的1.5倍頻電路來減少功率消耗以及減少電感使用，其功率消耗為 31.2 毫瓦 以及 -40dBc 內頻帶突刺的表現。 另外，我們又提出一個適合傳輸器整合的頻率合成器，此頻率合成器結合單一鎖相迴路以及單一延遲鎖定迴路。藉由使用數位形式的除頻器、改良的汲取電流式延遲細胞元(current-starved delay cell)之延遲鎖定迴路以及我們所提出的2倍頻電路，可以降低其功率消耗。利用65奈米CMOS製程，模擬結果顯示此頻率合成器消耗 19.2 毫瓦，為已有文獻中最小功率消耗之頻率合成器。In recent years, wireless communication act as a significant component in data transmission for consumer application. Ultra-Wideband (UWB) system is the next generation of wireless communication aimed to high transmission rate (480 Mbps) over short range (10m) and low power consumption. The MultiBand Orthogonal Frequency Division Multiplexing (MB-OFDM) proposed by the MultiBand OFDM Alliance (MBOA) seems to be mainly adopted. However, one of the most difficult challenges in MB-OFDM UWB system is frequency synthesizer. Although MBOA partitions the spectrum from 3 to 10 GHz into 14 bands with spacing of 528MHz, “Mode-1” composed of bands 1-3 has the highest economic value for market. The Single-Sideband (SSB) mixing architecture is commonly adopted although some different solutions are published. In this thesis, we develop the different architectures of MB-OFDM Mode-1 frequency synthesizer based on SSB mixer. Meanwhile, CMOS technology is chosen to implement the circuits for high-level integration and low-cost requirement. We propose the frequency synthesizer based on single PLL to eliminate the use of multiple PLLs, and it can significantly decrease the die area caused by loop filters. Meanwhile, the coupled VCO and coupled injection-locked divider can save the power consumption. Fabricated in TSMC 0.18μm CMOS process, the frequency synthesizer has -36dBc in-band spur performance with 65mW power consumption. For TSMC 0.13μm CMOS process, we furthermore propose multiply-by-1.5 circuit with current-reuse technique to less power dissipation and remove the use of inductor. In this chip, the power dissipation is 31.2mW and the in-band spur is -40dBc. We propose another frequency synthesizer which is fit to transceiver integration by combining one PLL and one DLL. It can reduce power consumption by the digital type divider, the delay locked loop with modified current-starved delay cells, and our proposed multiply-by-2 circuit. With 65nm CMOS process, the simulation results show our proposed work consumes 19.2mW and it has the lowest power-consumption among the published works.Abstract i Contents v List of Figures vii List of Tables xiii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Overview 2 Chapter 2 The Essentials of MB-OFDM UWB Frequency Synthesizer 3 2.1 Ultra-Wideband (UWB) System Overview 3 2.1.1 UWB System Introduction 3 2.1.2 MBOA Standard 5 2.2 Frequency Synthesizer 7 2.2.1 Operation Range and Switching Time 8 2.2.2 Phase Noise 8 2.2.3 Spur (Sideband) 9 2.3 MB-OFDM Mode-1 UWB Frequency Synthesizer 11 2.3.1 The Specifications and Challenges of MB-OFDM Mode-1 UWB Frequency Synthesizer 11 2.3.2 The Architectures of MB-OFDM Mode-1 UWB Frequency Synthesizer 13 Chapter 3 Single PLL Based MB-OFDM Mode-1 Frequency Synthesizer 19 3.1 The Proposed Synthesizer Architecture 20 3.2 The Injection Multiplier Circuit Based Frequency Synthesizer 22 3.2.1 Behavior Simulation 23 3.2.2 Circuit Implementation 24 3.2.3 Experimental Results 41 3.2.4 Performance Summary 45 3.3 The Current-Reuse Multiplier Circuit Based Frequency Synthesizer 46 3.3.1 Behavior Simulation 46 3.3.2 Circuit Implementation 47 3.3.3 Experimental Results 52 3.3.4 Performance Summary 57 3.4 Summary and Conclusion 58 Chapter 4 A MB-OFDM Mode-1 Frequency Synthesizer with PLL and DLL 59 4.1 The Proposed Synthesizer Architecture 60 4.2 Behavior Simulation 61 4.3 Circuit Implementation 63 4.3.1 PLL Circuit Implementation 63 4.3.2 DLL Circuit Implementation 67 4.3.3 The Multiply-by-2 Circuit Implementation 70 4.3.4 Total Simulation 74 4.4 Summary 76 Chapter 5 Conclusions 77 Bibliography 792953855 bytesapplication/pdfen-US頻率合成器超寬頻系統frequency synthesizerUWB systemthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57227/1/ntu-96-R94943082-1.pdf