Chang-Lin HsiehSHEN-IUAN LIU2018-09-102018-09-102011-1215497747http://scholars.lib.ntu.edu.tw/handle/123456789/366446https://www.scopus.com/inward/record.uri?eid=2-s2.0-83655167013&doi=10.1109%2fTCSII.2011.2172520&partnerID=40&md5=357f3c4e610b1befa3409c43cfab9c17A merged adder/D-type flip-flop (DFF) is presented by using the back-gate feedback technique. By using this merged adder/DFF, a slicerless one-tap decision feedback equalizer (DFE) and a cascaded DFE are fabricated in 65-nm CMOS technology. For a cable loss of 12 dB and a 30-Gb/s pseudorandom bit sequence (PRBS) of $2 {7} - 1$, the measured bit error rate of the slicerless one-tap DFE is below $10-11. Its power dissipation is 27 mW from a 1-V supply. For a cable loss of 12 dB and a 30-Gb/s PRBS of $2 {15} - 1$ , the measured bit error rate of the cascaded DFE is below $10-12. This cascaded DFE consumes 55 mW from a 1-V supply. © 2006 IEEE.Back gate; Channel loss; Decision feedback equalizer (DFE); Feedback; Intersymbol interference (ISI)Adders; Bit error rate; Cables; Feedback; Flip flop circuits; Back gates; Channel loss; CMOS technology; Feedback techniques; Pseudo random bit sequences; Decision feedback equalizersjournal article10.1109/TCSII.2011.21725202-s2.0-83655167013WOS:000298052500024