傅楸善臺灣大學：資訊工程學研究所王夏果Wang, Hsia-KuoHsia-KuoWang2007-11-262018-07-052007-11-262018-07-052007http://ntur.lib.ntu.edu.tw//handle/246246/53903CAVLC的全名為Context-Adaptive Variable Length Coding. Context-Adaptive的意義, 即在於對各種不同的context, 使用不同的table進行encode, 以針對各種情況有效縮短輸出bit stream長度。在H. 264中, CAVLC用於encode integer DCT (Discrete Cosine Transform) 轉換後的matrix係數。首先, CAVLC先擷取出目標matrix的非零coefficient總數、Trailing one (代表以zigzag方式從左上角開始, 反覆掃瞄所有非零coefficient時, 在尾端的+1或-1) 總數、等於0的coefficient總數、各zero run (以zigzag順序掃瞄時, 連續出現的0) 等參數, 作為查表時的index, 而非直接encode所有coefficient. 同時, CAVLC分別針對了不同的block type (4*4, 2*4, 2*2三種block) 設計了不同的table. 本篇論文提出了一種新的設計方式, 以公定規格之CAVLC為基礎, 進一步設計出節省計算時間、儲存空間, 同時具有最小面積之IC晶片。This paper proposes a new method of CAVLC (Context Adaptive Variable Length Coding) encoder design. To achieve best hardware utilization, this function is divided into 8 parts: Stage1, nCBuffer, LevelBuffer, writeSE_LEVEL_VLC, writeSE_Total0, writeSE_0Run, Mux_5to1, and OutputUnit. The memory cost is fewer with smaller buffer and carefully reduced lookup tables. Besides, the two-stage pipelined structure improves the data throughput. Thus, this design is suitable for the real-time H.264/AVC video encoding/decoding on digital cameras.目 錄 口試委員會審定書……………………………………………… i 誌謝……………………………………………………………… ii 中文摘要………………………………………………………… iii 英文摘要………………………………………………………… iv 目錄……………………………………………………………… v 圖錄……………………………………………………………… vi 表錄……………………………………………………………… vii Chapter 1 Introduction……………………………………… 1 Chapter 2 Background…………………………… 3 Chapter 3 Proposed Architecture………………………… 4 3.1 Stage1……………………………………………… 5 3.2 nCBuffer…………………………………………… 7 3.3 LevelBuffer……………………………………… 9 3.4 writeSE_LEVEL…………………………………… 11 3.5 writeSE_Total0………………………………… 14 3.6 writeSE_0Run…………………………………… 14 3.7 Mux_5to1………………………………………… 16 3.8 OutputUnit……………………………………… 17 3.9 CAVLC controller……………………………… 19 Chapter 4 Results………………………………………… 20 4.1 Time………………………………20 4.2 Space…………………………………………………………… 21 Chapter 5 Conclusion and Future Work………………………… 22 Chapter 6 Reference……………………………………………… 23 圖 錄 Fig. 1: Huffman Coding.......................................................................................1 Fig. 2: Zig-zag Scan................................................................................................3 Fig. 3: Architecture of proposed encoder................................................................4 Fig. 4: State diagram of Stage 1...............................................................................6 Fig. 5: I/O signals of Stage 1...................................................................................7 Fig. 6: I/O signals of nCBuffer.................................................................................9 Fig. 7: I/O signals of LevelBuffer...........................................................................10 Fig. 8: State diagram of writeSE_LEVEL.............................................................12 Fig. 9: Thresholds of level tables............................................................................13 Fig. 10: I/O signals of riteSE_LEVEL......................................................................13 Fig. 11: I/O signals of writeSE_Total0.......................................................................14 Fig. 12: I/O signals of writeSE_0Run........................................................................15 Fig. 13: I/O signals of Mux_5to1...............................................................................17 Fig. 14: I/O signals of OutputUnit..............................................................................18 Fig. 15: An instance of the best case..........................................................................20 Fig. 16: An instance of the worst case.......................................................................20 表 錄 Table 1: Choice of look-up tables for coeff_token.......................................................8 Table 2: Required clock rate for different video formats............................................20 Table 3: Comparison of gate counts...........................................................................21 Table 4: Memory and corresponding content.............................................................21en-US視訊編碼器管線架構H. 264CAVLCEncoderthesis